• The Journal of the Korea Contents Association
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• v.9 no.10
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• pp.67-74
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• 2009

Incorrect deployment of RFID readers occurs reader-to-reader interferences in many applications using RFID technologies. Reader-to-reader interference occurs when a reader transmits a signal that interferes with the operation of another reader, thus preventing the second reader from communicating with tags in its interrogation zone. Interference detected by one reader and caused by another reader is referred to as a reader collision. In RFID systems, the reader collision problem is considered to be the bottleneck for the system throughput and reading efficiency. In this paper, we propose a novel RFID reader anti-collision algorithm based on evolutionary algorithm(EA). First, we analyze characteristics of RFID antennas and build database. Also, we propose EA encoding algorithm, fitness algorithm and genetic operators to deploy antennas efficiently. To show superiority of our proposed algorithm, we simulated our proposed algorithm. In the result, our proposed algorithm obtains 95.45% coverage rate and 10.29% interference rate after about 100 generations.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.9
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• pp.37-43
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• 2010

An Interference Cancellation Wireless Repeater transmitts directly amplified the RF signal input to extend the coverage of the base station. Such a repeater inevitably suffers from the feedback interferences due to the environment and the adaptive Interference Cancelling System(ICS) is necessary. In this paper, the Variable Stepsize Complex Sign -Sign(VSCSS) LMS algorithm for ICS is presented. The algorithm can be implemented without multiplication/division arithmetic operation so that the required logic resources can be dramatically reduced in FPGA implementation. The performance of the proposed algorithm was analyzed in comparison with CSS-LMS algorithm and the learning curves obtained from simulation showed an excellent agreement with the theorical prediction. The simulation result with ICS in fading feedback channel environment showed the performance of the proposed algorithm is competible with NLMS algorithm.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.9
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• pp.44-53
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• 1999

Generating diagnostic test patterns for combinational circuits remain to be a very difficult problem. For example, ISCAS85 c7552 benchmark circuit has 100 million fault pairs, Thus, we need more sophisticated algorithm to get more information. A new diagnostic algorithm for test pattern generation is suggested and implemented in this paper. DIATEST algorithm based on PODEM is also implemented for comparison to the new algorithm. These two algorithms have been applied to ISCAS85 benchmark circuits. Experimental results show that (1) both algorithms achieve fault pair coverage over 99%, (2) total test length of the new algorithm is much shorter than that of DIATEST, and (3) the new algorithm gives much more information used for making diagnostic dictionary, diagnostic decision tree or diagnostic test system despite DIATEST is faster than the new algorithm.

• ETRI Journal
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• v.26 no.6
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• pp.520-534
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• 2004

As the density of memories increases, unwanted interference between cells and the coupling noise between bit-lines become significant, requiring parallel testing. Testing high-density memories for a high degree of fault coverage requires either a relatively large number of test vectors or a significant amount of additional test circuitry. This paper proposes a new tiling method and an efficient built-in self-test (BIST) algorithm for neighborhood pattern-sensitive faults (NPSFs) and new neighborhood bit-line sensitive faults (NBLSFs). Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a four-cell layout is utilized. This four-cell layout needs smaller test vectors, provides easier hardware implementation, and is more appropriate for both NPSFs and NBLSFs detection. A CMOS column decoder and the parallel comparator proposed by P. Mazumder are modified to implement the test procedure. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present algorithm properties such as the capability to detect stuck-at faults, transition faults, conventional pattern-sensitive faults, and neighborhood bit-line sensitive faults.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.71-76
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• 2007

The effect of crosstalk errors is most significant in high-performance circuits. This paper presents effective test patterns for SoC and Board level interconnects considering actual effective aggressors. Initially '6n' algorithm, where 'n' is the total number of interconnect nets, is analyzed to detect and diagnose 100% crosstalk faults. Then, more efficient algorithm is proposed reducing the number of test patterns significantly while maintaining complete crosstalk fault coverage.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.3
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• pp.990-1013
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• 2015

Deploying sensors into a target region is a key issue to be solved in building a wireless sensor network. Various deployment algorithms have been proposed by the researchers, and most of them are evaluated under the ideal conditions. Therefore, they cannot reflect the real environment encountered during the deployment. Moreover, it is almost impossible to evaluate an algorithm through practical deployment. Because the deployment of sensor networks require a lot of nodes, and some deployment areas are dangerous for human. This paper proposes a deployment approach to solve the problems mentioned above. Our approach relies on the satellite images and the Virtual Force Algorithm (VFA). It first extracts the topography and elevation information of the deployment area from the high resolution satellite images, and then deploys nodes on them with an improved VFA. The simulation results show that the coverage rate of our method is approximately 15% higher than that of the classical VFA in complex environment.

• Journal of Korea Multimedia Society
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• v.12 no.5
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• pp.728-736
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• 2009

We propose a method using the genetic algorithm to solve the maximum set cover problem. It is needed for scheduling the power of sensor nodes in extending the lifetime of the wireless sensor network with variable sensing range. The existing Greedy Heuristic method calculates the power scheduling of sensor nodes repeatedly in the process of operation, and so the communication traffic of sensor nodes is increased. The proposed method reduces the amount of communication traffic of sensor nodes, and so the energies of nodes are saved, and the lifetime of network can be extended. The effectiveness of this method was verified through computer simulation, and considering the energy losses of communication operations about 10% in the network lifetime is improved.

• The Journal of the Korea Contents Association
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• v.20 no.8
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• pp.637-644
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• 2020

VANET (Vehicular Ad Hoc Networks) is a network between vehicles and between vehicles and infrastructure. VANET-specific characteristics such as high mobility, movement limitation, and signal interference by obstacles make it difficult to provide stable VANET services. To solve this problem, this paper proposes a vehicle type-based priority clustering method that improves the existing bus-based clustering. The proposed algorithm constructs a cluster by evaluating the priority, link quality, and connectivity based on the vehicle type, expected communication lifetime, and link degree of neighbor nodes. It tries to simplify the process of selecting a cluster head and increase cluster coverage by utilizing a predetermined priority based on the type of vehicle. The proposed algorithm is expected to become the basis for activating various services by contributing to providing stable services in a connected car environment.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.1
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• pp.30-38
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• 2003

UDP library of Verilog HDL has been used for simulation of digital systems. But it takes a lot of time and efforts to generate a gate-level library equivalent to the UDP library manually due to the characteristic of UDP that does not support synthesis. It is indispensable to generate equivalent gate-level model in testing the digital systems because fault coverage can be reduced without the equivalent gate-level models. So, it is needed to automate the process of generating the equivalent gate-level models. An algorithm to solve this problem has been proposed, but it is unnecessarily complex and time-consuming. This paper suggests a new improved algorithm to implement the conversion to gate-level models, which exploits the characteristic of UDP Experimental results are demonstrated to show the effectiveness of the new algorithm.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.9
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• pp.53-60
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• 1997

In this paper, an efficient BILBO(named EBILBO) is proposed for batch testing application when a BIST (built-in self test) circuit is implemented on ASIC. In a large and complex circuit, the proposed algorithm of batch testing has one pin-count that can easily control 4 test modes in the normal speed of circuit operation. For the implementation of the BIST cifcuit, the test patern needed is generated by PRTPG(pseudo-random test pattern generator) and the ouput is observed by proposed algorithm is easily modified, such as the modelling of test pattern genration, signature EBILBO area and performance of the implemented BIST are evaluated using ISCAS89 benchmark circuits. As a resutl, in a circuit above 600 gates, it is confirmed that test patterns are genrated flexibly about 500K as EBILBO area is 59%, and the range of fault coverage is from 88.3% to 100%. And the optimized operation frequency of EBILBO designed and the area are 50MHz and 150K respectively. On the BIST circit of the proposed batch testing, the test mode of EBILBO is able to execute as realtime that has te number of s$\^$+/n$\^$+/(2s/2p-1) clocks simultaneously with the normal mode of circuit operation. Also the proposed algorithm is made of the library with VHDL coding thus, it will be widely applied to DFT (design for testability) that satisfies the design and test field.