• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.119-124
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• 2008

Transimpedance amplifier(TIA) is the most significant element to determine the performance of the optical receiver, and thus the TIA must satisfy tile design requirements of high gain and wide bandwidth. In f)is paper, we propose a novel single chip optical receiver that exploits an analog adaptive equalizer and a limiting amplifier to enhance the gain and bandwidth performance, respectively. The proposed optical receiver is designed by using a $0.13{\mu}m$ CMOS process and its post-layout simulations show $120dB{\Omgea}$ transimpedance gain and 5.88GHz bandwidth. The chip core occupies the area of $0.088mm^2$, due to utilizing the negative impedance converter circuit rather than using on-chip passive inductors.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.1005-1008
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• 2007

In this study, an architecture for 262K-color TFT-LCD source driver. In this paper proposed the chip consumes smaller area and static current which is suitable for QVGA resolutions. In the conventional structures, all of them need large number of OPAMP buffers to drive the pixels, Therefore, highly resistive R-DACs are needed to generate gamma voltages to reduce the static current. In this study, our design only used two OPAMPs and low resistance RDACs without increasing the quiescent current. Thus, it was experted that chip would be more in consuming lower static power for longer battery lifetime. The source driver were implemented by the 3.3 V $0.35\;{\mu}m$ CMOS technology provided by TSMC. The area of the core OPAMP circuit was about $110\;{\mu}m\;{\times}\;150\;{\mu}m$ and that of the source driver was $880\;{\mu}m\;{\times}\;430\;{\mu}m$. As compared to the conventional structure, approximately 64.48 % in area was achieved.

• Journal of the Korean Magnetics Society
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• v.18 no.1
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• pp.43-47
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• 2008

[ $ZnO-Bi_2O_3-Al_2O_3-B_2O_3-SiO_2$ ] nano-glass has been prepared by sol-gel method. The mean particle size was 60.3 nm with narrow size distribution. The nano-galss has been used as a sintering aid for the densification of the NiZnCu ferrites. The ferrite was sintered with nano-glass sintering aids at $840{\sim}900^{\circ}C$, 2 h and the initial permeability, quality factor, density, and saturation magnetization were also measured. The initial permeability of 0.5 wt% nano-glass added toroidal sample for NiZnCu ferrites sintered at $900^{\circ}C$ was 193.3 at 1 MHz. The initial permeability and saturation magnetization were increased with increasing annealing temperature. As a result, $ZnO-Bi_2O_3-Al_2O_3-B_2O_3-SiO_2$ nano-glass systems were found to be useful as sintering aids for multilayer chip inductors.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.28-34
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• 2011

In this paper, we present integer and fractional motion estimation IP for H.264/AVC encoder by hardware-oriented algorithm. In integer motion engine, the reference block is used to share for consecutive current macro blocks in parallel processing which exploits data reusability and reduces off-chip bandwidth. In fractional motion engine, instead of two-step sequential refinement, half and quarter pel are processed in parallel manner in order to discard unnecessary candidate positions and double throughput. The H.264/AVC motion estimation chip is fabricated on a MPW(Multi-Project Wafer) chip using the chartered $0.18{\mu}m$ standard CMOS 1P5M technology and achieves high throughput supporting HDTV 720p 30 fps.

• BioChip Journal
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• v.12 no.4
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• pp.332-339
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• 2018

The future neuro-prosthetic devices would be required spikes data monitoring through sub-nanoscale transistors that enables to neuroscientists and clinicals for scalable, wireless and implantable applications. This research investigates the spikes monitoring through integrated CNT front-end amplifier for neuro-prosthetic diagnosis. The proposed carbon nanotube-based architecture consists of front-end amplifier (FEA), integrate fire neuron and pseudo resistor technique that observed high electrical performance through neural activity. A pseudo resistor technique ensures large input impedance for integrated FEA by compensating the input leakage current. While carbon nanotube based FEA provides low-voltage operation with directly impacts on the power consumption and also give detector size that demonstrates fidelity of the neural signals. The observed neural activity shows amplitude of spiking in terms of action potential up to $80{\mu}V$ while local field potentials up to 40 mV by using proposed architecture. This fully integrated architecture is implemented in Analog cadence virtuoso using design kit of CNT process. The fabricated chip consumes less power consumption of $2{\mu}W$ under the supply voltage of 0.7 V. The experimental and simulated results of the integrated FEA achieves $60G{\Omega}$ of input impedance and input referred noise of $8.5nv/{\sqrt{Hz}}$ over the wide bandwidth. Moreover, measured gain of the amplifier achieves 75 dB midband from range of 1 KHz to 35 KHz. The proposed research provides refreshing neural recording data through nanotube integrated circuit and which could be beneficial for the next generation neuroscientists.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.3
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• pp.355-366
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• 2022

This paper proposes a microcode-based neural network accelerator controller for artificial intelligence accelerators that can be reconstructed using a programmable architecture and provide the advantages of low-power and ultra-small chip size. In order for the target accelerator to support various neural network models, the neural network model can be converted into microcode through microcode compiler and mounted on accelerator to control the operators of the accelerator such as datapath and memory access. While the proposed controller and accelerator can run various CNN models, in this paper, we tested them using the YOLOv2-Tiny CNN model. Using a system clock of 200 MHz, the Controller and accelerator achieved an inference time of 137.9 ms/image for VOC 2012 dataset to detect object, 99.5ms/image for mask detection dataset to detect wearing mask. When implementing an accelerator equipped with the proposed controller as a silicon chip, the gate count is 618,388, which corresponds to 65.5% reduction in chip area compared with an accelerator employing a CPU-based controller (RISC-V).

• Journal of IKEEE
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• v.11 no.4
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• pp.145-151
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• 2007

In this work, small-size, high-performance solenoid-type RF chip inductors utilizing a low-loss ${Al_2}{O_3}$ core material were investigated. The size of the chip inductors fabricated in this work were $0.86{\times}0.46{\times}0.45m^3$, $1.5{\times}1.0{\times}0.7m^3$, $2.1{\times}1.5{\times}1.0m^3$, and $2.4{\times}2.0{\times}1.4m^3$ and copper (Cu) wire with $27{\sim}40{\mu}m$ diameter was used as the coils. High frequency characteristics of the inductance, quality factor, and impedance of developed inductors were measured using an RF Impedance/Material Analyzer (HP4291B with HP16193A test fixture). It was observed that the developed inductors with the number of turns of 7 have the inductance of 13 to 100nH and exhibit the self-resonant frequency (SRF) of 6.4 to 1.1GHz. The SRF of inductors decreases with increasing the inductance and the inductors have the quality factor of 50 to 80 in the frequency range of 300MHz to 1.3GHz. In this study, small-size solenoid-type RF chip inductors with high inductance and high quality factor were fabricated successfully.

• Tuberculosis and Respiratory Diseases
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• v.50 no.1
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• pp.29-41
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• 2001

Background : The appearance of multiple-drug-resistant Mycobacterium tuberculosis strains has been seriously compromising successful control of tuberculosis. Rifampin-resistance, caused by mutations in the rpoB gene, can be indicative of multiple-drug-resistance, and its detection is of great importance. The present study aimed to develop an oligonucleotide chip for accurate and convenient screening of drug-resistance. Methods : In order to detect point mutations in the rpoB gene, an oligonucleotide chip was prepared by immobilizing specific probe DNA to a microscopic slide glass by a chemical reaction. The probe DNA that was selected from the 81 bp core region of the rpoB gene was designed to have mutation sites at the center. A total of 17 mutant probes related to rifampin-resistance including 8 rifabutin-sensitive mutant probes were used in this study. For accurate determination, wild type probes were prepared for each mutation position with an equal length, which enabled a direct comparison of the hybridization intensities between the mutant and wild type. Results : Mycobacterial genomic DNA from clinical samples was tested with the oligonucleotide chip and the results were compared with those of the drug-susceptibility test in addition to sequencing and INNO-LiPA Rif. TB kit test in some cases. Out of 15 samples, the oligonucleotide chip results of 13 samples showed good agreement with the rifabutin-sensitivity results. The two samples with conflicting result also showed a discrepancy between the other tests, suggesting such possibilities as existence of mixed strains and difference in drug-sensitivity. Further verification of these samples in addition to more case studies are required before the final evaluation of the oligonucleotide chip can be made. Conlcusion : An oligonucleotide chip was developed for the detection of rpoB gene mutations related to drugsusceptibility. The results to date show the potential for using the oligonucleotide chip for accurate and convenient screening of drug-resistance to provide useful information in antituberculosis drug therapy.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.286-292
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• 2012

Scan techniques are almost mandatorily adopted in designing current System-on-a-Chip (SoC) to enhance testability, but inadvertently secret keys can be stolen through the scan test channels of crypto SoCs. An efficient scan design technique is proposed in this paper to protect the secret key of an Advanced Encryption Standard (AES) core embedded in an SoC. A new instruction is added to IEEE 1149.1 boundary scan to use a fake key instead of user key, in which the fake key is chosen with meticulous care to improve the testability as well. Our approach can be implemented as user defined logic with conventional boundary scan design, hence no modification is necessary to any crypto IP core. Conformance to the IEEE 1149.1 standards is completely preserved while yielding better performance of area, power, and fault coverage with highly robust protection of the secret user key.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.10
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• pp.2136-2149
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• 1997

This paper describes RISC core that has been designed for embedded and protable applications such as PDA or PCS. This RISC processor offers low power consumption and fast context switching. Processor performance is improved by using conditional instruction execution, block data transfer instruction, and multiplication instruction. This architecture is based on RISC principles. The processor adopts 3-stage instruction execution pipeline and has achieved single cycle execution using a 2-phase 40MHz clock. This results in a high instruction throughput and real-time interrupt response. This chip is implemented with $0.6{\mu}m$ triple metal CMOS technology and consists of about 88K transistors. The estimated power dissipation is 179mW.