• Journal of IKEEE
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• v.25 no.1
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• pp.229-233
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• 2021

NPU in an embedded environment performs deep learning algorithms with few hardware resources. By using a technique that reuses data, deep learning algorithms can be efficiently computed with fewer resources. In previous studies, data is reused using a shifter in ScratchPad for data reuse. However, as the ScratchPad's bandwidth increases, the shifter also consumes a lot of resources. Therefore, we present a data reuse technique using the Buffer Round Robin method. By using the Buffer Round Robin method presented in this paper, the chip area could be reduced by about 4.7% compared to the conventional method.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.59-63
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• 2013

In this paper, the impact of the copper densities of substrate layers on IC package warpage is studied experimentally and numerically. The substrate strips used in this study contained two metal layers, with the metal densities and patterns of these two layers varied to determine their impacts. Eight legs of substrate strips were prepared. Leg 1 to leg 5 were prepared with a HD (high density) type of strip and leg 6 to leg 8 were prepared with UHD (ultra high density) type of strip. The top copper metal layer was designed to feature meshed patterns and the bottom copper layer was designed to feature circular patterns. In order to consider the process factors, the warpage of the substrate bottom was measured step by step with the following manufacturing process: (a) bare substrate, (b) die attach, (c) applying mold compound (d) and post reflow. Furthermore, after the post reflow step, the substrate strips were diced to obtain unit packages and the warpage of the unit packages was measured to check the warpage trends and differences. The experimental results showed that the warpage trend is related to the copper densities. In addition to the experiments, a Finite Element Modeling (FEM) was used to simulate the warpage. The nonlinear material properties of mold compound, die attach, solder mask, and substrate core were included in the simulation. Through experiment and simulation, some observations were concluded.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.3
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• pp.454-459
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• 2007

In this work, micro-scale, high-performance solenoid-type RF chip inductors utilizing amorphous $Al_2O_3$ core material were investigated. The size of the chip inductors was $0.86{\times}0.46{\times}0.45mm^3$ and copper(Cu) wire with $27{\mu}m$ diameter was used as the coil. High frequency characteristics of the inductance(L), quality factor(Q), impedance(Z), and equivalent circuit parameters of the RE chip inductors were measured and analyzed using an RF impedance/material analyzer(HP4291B with HP16193A test fixture). It was observed that the RF chip inductors with the number of turns of 9 to 12 have the inductance of 21 to 34nH and exhibit the self-resonant frequency(SRF) of 5.7 to 3.7GHz. The SRF of inductors decreases with increasing the inductance and inductors have the quality factor of 38 to 49 in the frequency range of 900MHz to 1,7GHz.

• ETRI Journal
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• v.42 no.4
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• pp.491-504
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• 2020

We present AB9, a neural processor for inference acceleration. AB9 consists of a systolic tensor core (STC) neural network accelerator designed to accelerate artificial intelligence applications by exploiting the data reuse and parallelism characteristics inherent in neural networks while providing fast access to large on-chip memory. Complementing the hardware is an intuitive and user-friendly development environment that includes a simulator and an implementation flow that provides a high degree of programmability with a short development time. Along with a 40-TFLOP STC that includes 32k arithmetic units and over 36 MB of on-chip SRAM, our baseline implementation of AB9 consists of a 1-GHz quad-core setup with other various industry-standard peripheral intellectual properties. The acceleration performance and power efficiency were evaluated using YOLOv2, and the results show that AB9 has superior performance and power efficiency to that of a general-purpose graphics processing unit implementation. AB9 has been taped out in the TSMC 28-nm process with a chip size of 17 × 23 ㎟. Delivery is expected later this year.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.128-133
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• 2008

Phase-change random access memory (PRAM) chip cell phase of amorphous state is rapidly changed to crystal state above 160 Celsius degree within several seconds during Infrared (IR) reflow. Thus, on-board programming method is considered for PRAM chip programming. We demonstrated the functional 512Mb PRAM with 90nm technology using several novel core circuits, such as metal-2 line based global row decoding scheme, PN-diode cells based BL discharge (BLDIS) scheme, and PMOS switch based column decoding scheme. The reverse-state standby current of each PRAM cell is near 10 pA range. The total leak current of 512Mb PRAM chip in standby mode on discharging state can be more than 5 mA. Thus in the proposed BLDIS control, all bitlines (BLs) are in floating state in standby mode, then in active mode, the activated BLs are discharged to low level in the early timing of the active period by the short pulse BLDIS control timing operation. In the conventional sense amplifier, the simultaneous switching activation timing operation invokes the large coupling noise between the VSAREF node and the inner amplification nodes of the sense amplifiers. The coupling noise at VSAREF degrades the sensing voltage margin of the conventional sense amplifier. The merit of the proposed sense amplifier is almost removing the coupling noise at VSAREF from sharing with other sense amplifiers.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.5
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• pp.325-335
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• 2018

We herein present a study on the active phased array antenna for receiving satellite broadcasting that can electrically align its polarization to that of target transmitters in its moving condition or in the Skew angle arrangement of the broadcasting satellite receiver. Hence, we have developed an active phased array structure composed of the self-developed Vivaldi antenna and multifunction core (MFC) chip, receiving RF front end module, and control units. In particular, the new Vivaldi antenna designed in the Ku-band of 10.7 - 14.5 GHz to receive one desired polarization mode such as the horizontal or vertical by means of an MFC chip and other control units that can control the amplitude and phase of each antenna element. The test results verified that cross-polarization property is 20 dB or higher and the primary beam can be scanned clearly at approximately ${\pm}60^{\circ}$.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.651-654
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• 2005

In this paper, we designed ECC(Elliptic Curve Cryptographic) Processor with Bus-splitting mothod for embedded SoC. ECC SIP is designed by VHDL RTL modeling, and implemented reusably through the procedure of logic synthesis, simulation and FPGA verification. To communicate with ARM9 core and SIP, we designed SIP bus functional model according to AMBA AHB specification. The design of ECC Processor for platform-based SoC is implemented using the design kit which is composed of many devices such as ARM9 RISC core, memory, UART, interrupt controller, FPGA and so on. We performed software design on the ARM9 core for SIP and peripherals control, memory address mapping and so on.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.11b
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• pp.1281-1284
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• 2002

본 논문은 인터넷을 이용한 음성통신 서비스를 제공하기 위해 사용되는 VoIP 시스템 칩 설계 및 기능 검증을 위한 보드 개발에 관한 것이다. 구성이 간단한 시스템을 구현하기 위하여 32 비트 RISC 프로세서인 ARM922T 프로세서 코어를 중심으로 IP 망 접속 기능, 톤 발생 및 음성신호 접속기능과 다양한 사용자 정합 기능을 가지는 VoIP 시스템 칩을 설계하고, 이 칩의 기능을 검증하기 위하여 시험 프로그램 및 통신 프로토콜을 개발하였으며, 각종 설계 및 시뮬레이션 툴을 사용하고 ARM922T와 FPGA가 결합된 Excalibur를 사용한 시험용 보드를 개발하여 시험하였다.

• Current Photovoltaic Research
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• v.4 no.4
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• pp.140-144
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• 2016

In this paper, core-shell structure of nickel/gold (Ni/Au) conductive layer on poly-methyl-methacrylate (PMMA) micro-ball was fabricated and its conduction property was investigated. Firstly, PMMA micro-ball was synthesized by using dispersion polymerization method. Size of the ball was $2.8{\mu}m$ within ${\pm}7%$ deviation, and appropriate elastic deformation of the PMMA micro-ball ranging from 31 to 39% was achieved under 3 kg pressure. Also, 200 nm thick Ni/Au conductive layer was fabricated on the PMMA micro-ball by uniformly depositing with electroless-plating. Adhesion of the conductive layer was optimized with help of surface pre-treatment, and the layer adhered without peeling-off despite of thermal expansion by collision with accelerated electrons. Composite paste containing core-shell structured particles well cured at low temperature of $130^{\circ}C$ while pressing the test chip onto the substrate to make electrical contact, and electrical resistance of the conductive layer showed stable behavior of about $6.0{\Omega}$. Thus, it was known that core-shell structured particle of the Ni/Au conductive layer on PMMA micro-ball was feasible to flexible electronics.

• Journal of Korea Society of Digital Industry and Information Management
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• v.15 no.4
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• pp.31-40
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• 2019

This paper proposes an adaptive PCIe system for TI C66x DSPs. Conventionally, the PCIe system provided by the C66x is a system dependent on the structure in which the primary core writes an application to the DSP memory through the PCIe interface, then activate the secondary core. Due to the dependency between the cores, when developing a project using a PCIe interface, the remaining cores have to be programmed with a concern of the primary core used as the PCIe interface. Therefore, in order to de-couple the connections among the cores, an adaptive PCIe system is proposed, in the paper, in which the cores operate independently compared to the conventional system. Since the core used as the PCIe interface only runs PCIe related operations in the new system, the remaining cores can be fully utilized without concerning the connections with the core for PCIe interface. In order to verify the feasibility of the proposed adaptive PCIe system, the implementations of LTE-A down link, and IEEE 802.11ac are carried out using the evaluation board which includes a TMS320C6670 chip. Altogether, these results support that we demonstrated that the digital signal processing systems with the PCIe Interface can be developed more rapidly by applying the proposed system.