Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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Low-area DNN Core using data reuse technique

데이터 재사용 기법을 이용한 저 면적 DNN Core

  • Jo, Cheol-Won (Dept. of Electronic and Computer Eng., Seokyeong University) ;
  • Lee, Kwang-Yeob (Dept. of Electronic and Computer Eng., Seokyeong University) ;
  • Kim, Chi-Yong (Dept. of Software, Seokyeong University)
  • Received : 2021.01.13
  • Accepted : 2021.03.22
  • Published : 2021.03.31
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Abstract

NPU in an embedded environment performs deep learning algorithms with few hardware resources. By using a technique that reuses data, deep learning algorithms can be efficiently computed with fewer resources. In previous studies, data is reused using a shifter in ScratchPad for data reuse. However, as the ScratchPad's bandwidth increases, the shifter also consumes a lot of resources. Therefore, we present a data reuse technique using the Buffer Round Robin method. By using the Buffer Round Robin method presented in this paper, the chip area could be reduced by about 4.7% compared to the conventional method.

임베디드 환경에서의 NPU는 적은 하드웨어 자원으로 딥러닝 알고리즘을 수행한다. 데이터를 재사용하는 기법을 활용하면 적은 자원으로 딥러닝 알고리즘을 효율적으로 연산할 수 있다. 선행연구에서는 데이터 재사용을 위해 ScratchPad에서 shifter를 사용해 데이터를 재사용한다. 하지만 ScratchPad의 Bandwidth가 커짐에 따라 shifter 역시 많은 자원을 소모한다. 따라서 Buffer Round Robin방식을 사용한 데이터 재사용 기법을 제시한다. 본 논문에서 제시하는 Buffer Round Robin 방식을 사용하여 기존의 방식보다 약 4.7%의 Chip Area를 줄일 수 있었다.

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References

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