• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.28 no.5
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• pp.52-59
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• 2014

This paper presents an improved operating characteristics of squirrel-cage induction motor(IM) for 5-phase 1.5kW, 220V, 60Hz in order to study a polyphase AC machinery that keep hold of advantages more than traditional three-phase a IM, such as reducing a amplitude of torque pulsation, decreasing electric noises, and increasing the reliability. The developed manufacturing motor was necessary to do improvement of speed regulation, efficiency, operating characteristics, and so on at rated load. There are remake a redesigned and distributed stator winding connection without changing the frames of stator and rotor core in previous established the motor by a repeat tests. There are shown a experiments results of no-load test, locked rotor test, operating characteristics at variable load, FFT analysis of harmonics within output voltages and current waveform, decided motor parameters.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.27 no.9
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• pp.53-61
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• 2013

This paper propose a improved operating characteristics of the 5-phase 5kW within developed the surface permanent mount synchronous generator (SPMSG) in order to make a study of a polyphase ac motors keeping hold of more advantages. The developed manufacturing motor was necessary to do improvement of voltage regulation, efficiency, operating characteristics, and so on at the rated load. There are remake a redesigned and distributed stator winding connection without changing the frames of stator and rotor core in previous established generator by a repeat tests. There are shown a amplitude and waveform of the generated electromotive force, FFT analysis of harmonics within output voltages, and reviewing a experiment results in load of resistive and 5-phase induction motor by variable generator output frequency.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.1
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• pp.50-55
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• 2007

In this paper, we present an analytical method that provides fast and efficient evaluation of the conversion efficiency for Two transistor forward (TTF) DC-DC converter In the proposed method, the conduction losses are evaluated by calculating the effective values of the ideal current waveform first and incorporating them into an exact equivalent circuit model of the TTF converter that includes all the parasitic resistances of the circuit components. While the conduction losses are accurately accounted for the diode rectification, the core losses are assumed to be negligible in order to simplify the analysis. The validity and accuracy of the proposed method are verified with experiments on a prototype TTF converter An excellent correlation between the experiments and theories are obtained for the input voltages of 390V, output voltage 12V and maximum power 480W.

• Transactions on Electrical and Electronic Materials
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• v.11 no.1
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• pp.20-23
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• 2010

The analog front end (AFE) of a radio frequency identification transponder using the ISO 14443 type A standard with a 100% amplitude shift keying (ASK) modulation is proposed in this paper and verified by circuit simulations and measurements. This AFE circuit, using a 13.56 MHz carrier frequency, consists of a rectifier, a modulator, a demodulator, a regulator, a power on reset, and a dynamically enabled digital phase locked loop (DPLL). The DPLL, with a charge pump enable circuit, was used to recover the clock of a 100% modulated ASK signal during the pause period. A high voltage lateral double diffused metal-oxide semiconductor transistor was used to protect the rectifier and the clock recovery circuit from high voltages. The proposed AFE was fabricated using the $0.18\;{\mu}m$ standard CMOS process, with an AFE core size of $350\;{\mu}m\;{\times}\;230\;{\mu}m$. The measurement results show that the DPLL, using a demodulator output signal, generates a constant 1.695 MHz clock during the pause period of the 100% ASK signal.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1868-1876
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• 2010

In this paper, we design a 256-bit EEPROM IP using only logic process-based devices. We propose EEPROM core circuits, a control gate (CG) and a tunnel gate (TG) driving circuit, to limit the voltages between the devices within 5.5V; and we propose DC-DC converters : VPP (=+4.75V), VNN (-4.75V), and VNNL (=VNN/3) generation circuit. In addition, we propose switching powers, CG_HV, CG_LV, TG_HV, TG_LV, VNNL_CG, VNNL_TG switching circuit, to be supplied for the CG and TG driving circuit. Simulation results under the typical simulation condition show that the power consumptions in the read, erase, and program mode are $12.86{\mu}W$, $22.52{\mu}W$, and $22.58{\mu}W$ respectively. Furthermore, the manufactured test chip operated normally and generated its target voltages of VPP, VNN, and VNNL as 4.69V, -4.74V, and -1.89V.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.11
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• pp.690-695
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• 2014

In this paper, we develop a explosion-proof LED lighting (Ex circuit) circuit of Explosion-proof LED Signal Lamp (Ex LSL) to utilize the core module of the explosion-proof Local Control System (Ex LCS) for offshore plant applications. And then analyzed its electrical, optical and thermal characteristics. Ex circuit was applied input voltage from AC/DC(12~254) V. In this experiments, stable light-on characteristics were confirmed by eyes for the every input voltages with min. 78,462 and max. $517,975cd/m^2$ of luminance. also Output current and output luminance was made proportional. Because the measured maximum surface temperature of Ex circuit was $54.23^{\circ}C$ at AC 48 V, Ex circuit was rated with T6 of temperature class. Finally, Ex circuit was shown stable light on characteristics under the $-50^{\circ}C$ and $60^{\circ}C$ during 12 hours of test period.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.1
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• pp.113-117
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• 2008

We investigated the current limiting and the recovery characteristics of a flux-lock type superconducting fault current limiter(SFCL) according to the winding directions. The flux-lock type SFCL consists of two coils. The primary coil was wound in parallel to the secondary coil through an Iron core, and the secondary coil was connected with the superconducting element in series. We have changed the winding direction of coils to compare the resistive type SFCL with the flux-lock type SFCL. The current limiting and the recovery characteristics were dependent on the winding direction. The quenching time in the additive polarity winding was faster than that of the subtractive polarity winding or the resistivity type. A consumed energy in a superconducting element was represented as $W= VIt=I^2Rt$. We found that there was a difference in the consumed energies in accordance with winding types because of differences in voltages imposed on a superconducting element in accordance with a winding direction.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.3
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• pp.228-234
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• 2009

In this paper, we present an analytical method that provides fast and efficient evaluation of the power losses and the conversion efficiency for phase-shift controlled full-bridge converter. In the proposed method, the conduction losses are evaluated by calculating the effective values of the ideal current waveform first and incorporating them into an exact equivalent circuit model of the phase-shift controlled full-bridge converter that includes all the parasitic resistances of the circuit components. While the conduction losses are accurately accounted for the synchronous rectification, the core losses are assumed to be negligible in order to simplify the analysis. The validity and accuracy of the proposed method are verified with experiments on a prototype phase-shift controlled full-bridge converter. An excellent correlation between the experiments and theories are obtained for the input voltages of 400V, output voltage 12V and maximum power 720W.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.1005-1008
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• 2007

In this study, an architecture for 262K-color TFT-LCD source driver. In this paper proposed the chip consumes smaller area and static current which is suitable for QVGA resolutions. In the conventional structures, all of them need large number of OPAMP buffers to drive the pixels, Therefore, highly resistive R-DACs are needed to generate gamma voltages to reduce the static current. In this study, our design only used two OPAMPs and low resistance RDACs without increasing the quiescent current. Thus, it was experted that chip would be more in consuming lower static power for longer battery lifetime. The source driver were implemented by the 3.3 V $0.35\;{\mu}m$ CMOS technology provided by TSMC. The area of the core OPAMP circuit was about $110\;{\mu}m\;{\times}\;150\;{\mu}m$ and that of the source driver was $880\;{\mu}m\;{\times}\;430\;{\mu}m$. As compared to the conventional structure, approximately 64.48 % in area was achieved.

• Proceedings of the KIEE Conference
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• 2003.07b
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• pp.723-725
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• 2003

The result of design and Partial fabrication of a 1 MVA single phase high temperature superconducting(HTS) transformer for power distributions are presented in this paper. The HTS windings are wound as double pancake windings which have advantages of uniform distribution of high voltage over the windings. the rated primary and secondary voltages are 22.9 kV and 6.6 kV respectively. Four HTS tapes are wound in parallel for secondary windings considering the rated currents of the transformer. The HTS windings will be cooled down to 65 K by natural convection of sub-cooled liquid nitrogen using a single-staged GM-cryocooler in order to make the stability of the HTS windings better. The iron core is designed as shell type and isolated from the liquid nitrogen by an FRP cryostat which have a room temperature bore. After the complete fabrication of the total HTS transformer system, performance test of the transformer will be carried out.