• Progress in Superconductivity and Cryogenics
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• v.14 no.1
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• pp.4-7
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• 2012

Coated conductors have been developed to increase piece length and critical current for electric power applications. Otherwise, Many efforts were carried out to reduce AC loss of coated conductor for AC applications. Twisting and cabling processes are effective to reduce AC loss but, these processes can not be applied for tape shaped coated conductor. It is inevitable to have thin rectangular shape because coated conductor is fabricated by thin film deposition process on metal substrate. In this study, round shape superconducting wire was first fabricated using coated conductors. First of all, Ag coated conductor was used. coated conductor was slitted to several wires with narrow width below 1mm. 12ea slitted wires were parallel stacked on top of another until making up the square cross-section. The bundle of coated conductors was heat treated to stick on each other by diffusion bonding and then copper plated to make round shape wire. Critical current of round wire was measured 185A at 77K, self field.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.27 no.9
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• pp.1-5
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• 2013

We developed high-efficient 6W-LED package with simple structure by applying Heat Slug and silicone-reflector. LED package was manufactured in $8.5{\times}8.5mm$ sized multi-chip structure having thickness of $500{\mu}m$ achieved by bonding silicon-reflector with prepreg on top of the plate after implementing the reflector placed on copper substrate Half Etching by thickness of $200{\mu}m$. The luminous flux, luminous efficacy, correlated color temperature, color rendering index and thermal resistance of developed LED was evaluated, and it verified the application of products by applying it to 120W-LED road luminaires through simulation. The luminous efficacy of LED package reached over 130lm/W, and it is possible to be manufactured into 120W-LED road luminaires using 18 packages. In addition, the simulation results showed average of horizontal illuminance and overall illuminance uniformity that is suitable for three-lane road.

• Korean Journal of Materials Research
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• v.30 no.7
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• pp.327-332
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• 2020

Laser induced surface activation (LISA) technology requires refined selection of process variables to fabricate conductive microcircuits on a general polymer material. Among the process variables, laser mode is one of the crucial factors to make a reliable conductor pattern. Here we compare the continuous wave (CW) laser mode with the pulse wave (PW) laser mode through determination of the surface roughness and circuit accuracy. In the CW laser mode, the surface roughness is pronounced during the implementation of the conductive circuit, which results in uneven plating. In the PW laser mode, the surface is relatively smooth and uniform, and the formed conductive circuit layer has few defects with excellent adhesion to the polymer material. As a result of a change of laser mode from CW to PW, the value of Ra of the polymer material decreases from 0.6 ㎛ to 0.2 ㎛; the value of Ra after the plating process decreases from 0.8 ㎛ to 0.4 ㎛, and a tight bonding force between the polymer source material and the conductive copper plating layer is achieved. In conclusion, this study shows that the PW laser process yields an excellent conductive circuit on a polymeric material.

• Journal of the Korea Institute of Military Science and Technology
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• v.26 no.3
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• pp.302-312
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• 2023

This paper describes the analysis of lightning strike zoning, the indirect lightning data simulation and the protection design for lightning indirect effects of equipment by lightning strike for unmanned aircraft consisting of composite wings. Through the analysis of lightning strike zoning according to the external shape of unmanned aerial vehicles, the structure areas that should be protected during lightning strike is derived, and the protection requirements of lightning indirect effects for flight critical equipments and equipment that must be operated upon lightning strike was derived. Lightning protection levels according to the location of mounting equipment and surrounding structure materials for each equipment was derived, and the protection design of the unmanned aerial vehicle with composite structures was also proposed from direct effect of lightning. Later, the lightning protection technology will be verified by the ground test of lightning direct and indirect effects.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.2
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• pp.79-84
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• 2016

A flexible electronic device deformed by external force causes the failure of a semiconductor die. Even without failure, the repeated elastic deformation changes carrier mobility in the channel and increases resistivity in the interconnection, which causes malfunction of the integrated circuits. Therefore it is desirable that a semiconductor die be placed on a neutral line where the mechanical stress is zero. In the present study, we investigated the effects of design factors on the position of neutral line by finite element analysis (FEA), and expected the possible failure behavior in a flexible face-down packaging system assuming flip-chip bonding of a silicon die. The thickness and material of the flexible substrate and the thickness of a silicon die were considered as design factors. The thickness of a flexible substrate was the most important factor for controlling the position of the neutral line. A three-dimensional FEA result showed that the von Mises stress higher than yield stress would be applied to copper bumps between a silicon die and a flexible substrate. Finally, we suggested a designing strategy for reducing the stress of a silicon die and copper bumps of a flexible face-down packaging system.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.2
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• pp.41-48
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• 2018

The quantitative interfacial adhesion energy measurement method of copper redistribution layer and WPR dielectric interface were investigated using $90^{\circ}$ peel test, 4-point bending test, double cantilever beam (DCB) measurement for FOWLP Applications. Measured interfacial adhesion energy values of all three methods were higher than $5J/m^2$, which is considered as a minimum criterion for reliable Cu/low-k integration with CMP processes without delamination. Measured energy values increase with increasing phase angle, that is, in order of DCB, 4-point bending test, and $90^{\circ}$ peel test due to increasing roughness-related shielding and plastic energy dissipation effects, which match well interfacial fracture mechanics theory. Considering adhesion specimen preparation process, phase angle, measurement accuracy and bonding energy levels, both DCB and 4-point bending test methods are recommended for quantitative adhesion energy measurement of RDL interface depending on the real application situations.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.1
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• pp.69-74
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• 2015

With difficulties during the cleaning of reflow flux residues due to the decrease of the part size and interconnection pitch in the advanced electronic devices, the need for the no-clean solder paste is increasing. In this study, an epoxy curable solder paste was made with SAC305 solder powder and the curable flux of which the main ingredient is epoxy resin and its reflow solderability, flux residue corrosivity and solder joint mechanical properties was investigated with comparison to the commercial rosin type solder paste. The fillet shape of the cured product around the reflowed solder joint revealed that the curing reaction occurred following the fluxing reaction and solder joint formation. The copper plate solderability test result also revealed that the wettability of the epoxy curable solder paste was comparable to those of the commercial rosin type solder pastes. In the highly accelerated temperature and humidity test, the cured product residue of the curable solder paste showed no corrosion of copper plate. From FT-IR analysis, it was considered to be resulted from the formation of tight bond through epoxy curing reaction. Ball shear, ball pull and die shear tests revealed that the adhesive bonding was formed with the solder surface and the increase of die shear strength of about 15~40% was achieved. It was considered that the epoxy curable solder paste could contribute to the improvement of the package reliability as well as the removal of the flux residue cleaning process.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.5
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• pp.283-288
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• 2000

In this work, small-size, high-performance simple solenoid-type RF chip inductors utilizing an Al2O3 core material were investigated. Copper (Cu) wire with $40\mum$ diameter was used as the coils and the size of the chip inductor fabricated in this work was $2.1mm\times1.5mm\times1.0mm$. The external current source was applied after bonding Cu coil leads to gold pads electro-plated on each end of backsides of a core material. High frequency characteristics of the inductance (L), quality factor (Q), and impedance (Z) of developed inductors were measured using an RF Impedance/Material Analyzer (HP4291B with HP16193A test fixture). This HP4291B was also used to obtain the equivalent circuit and its circuit parameters of the chip inductors. This HP4291B was also used to obtain the equivalent circuit and its circuit parameters of the chip inductors. The developed inductors have the self-resonant frequency (SRF) of 1.1 to 3.1 GHz and exhibit L of 22 to 150 nH. The L of the inductors decreases with increasing the SRF. The Z of the inductors has the maximum value at the SRF and the inductors have the quality factor of 70 to 97 in the frequency range of 500 MHz to 1.5 GHz.

• Journal of Surface Science and Engineering
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• v.50 no.3
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• pp.170-176
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• 2017

EPIG (Electroless Pd/immersion Au) process was studied to replace ENIG (electroless Ni/immersion Au) and ENEPIG (electroless Ni/electroless Pd/immersion Au) processes for bump surface treatment used in high reliable flip chip packages. The palladium and gold layers formed by EPIG process were uniform with thickness of 125 nm and 34.5 nm, respectively. EPAG (Electroless Pd/autocatalytic Au) also produced even layers of palladium and gold with the thickness of 115 nm and 100 nm. TEM results exhibited that the gold layer in EPIG surface had crystalline structure while the palladium layer was amorphous one. After annealing at 250 nm, XPS analysis indicated that the palladium layer with thickness more than 22~33 nm could act as a diffusion barrier of copper interconnects. As a result of comparing the chip shear strength obtained from ENIG and EPIG surfaces, it was confirmed that the bonding strength was similar each other as 12.337 kg and 12.330 kg, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.112-117
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• 2008

Vertical interconnection scheme using novel silicon-through-via for 3D MEMS devices or stacked package is proposed and fabricated to demonstrate its feasibility. The suggested silicon-through-via replaces electroplated copper, which is used as an interconnecting material in conventional through-via, with doped silicon. Adoption of doped silicon instead of metal eliminates thermal-mismatch-induced stress, which can make troubles in high temperature MEMS processes, such as wafer bonding and LP-CVD(low pressure chemical vapor deposition). Two silicon layers of $30{\mu}m$ thickness are stacked on the substrate. The through-via arrays with spacing $40{\mu}m$ and $50{\mu}m$ are fabricated successfully. Electrical characteristics of the through-via are measured and analyzed. The measured resistance of the silicon-through-via is $169.9\Omega$.