• IEIE Transactions on Smart Processing and Computing
• /
• 제4권4호
• /
• pp.291-296
• /
• 2015

This paper describes the design of a high-speed comparator for high-speed automatic test equipment (ATE). The normal comparator block, which compares the detected signal from the device under test (DUT) to the reference signal from an internal digital-to-analog converter (DAC), is composed of a rail-to-rail first pre-amplifier, a hysteresis amplifier, and a third pre-amplifier and latch for high-speed operation. The proposed continuous comparator handles high-frequency signals up to 800MHz and a wide range of input signals (0~5V). Also, to compare the differences of both common signals and differential signals between two DUTs, the proposed differential mode comparator exploits one differential difference amplifier (DDA) as a pre-amplifier in the comparator, while a conventional differential comparator uses three op-amps as a pre-amplifier. The chip was implemented with $0.18{\mu}m$ Bipolar CMOS DEMOS (BCDMOS) technology, can compare signal differences of 5mV, and operates in a frequency range up to 800MHz. The chip area is $0.514mm^2$.

• 한국산업정보학회논문지
• /
• 제19권3호
• /
• pp.1-7
• /
• 2014

본 논문은 자동시험장비 (ATE) 시스템의 측정 회로에 사용하는 비교기 설계에 관한 것이다. 이 비교기 전체 블럭은 연속 형의 고속 비교기, 차동차이증폭기, 그리고 출력 단으로 구성되어 있다. 연속 형의 고속 비교기는 높은 주파수(1~800MHz) 및 넓은 범위(0~5V)의 입력신호를 받아들이기 위해, 고속의 rail-to-rail 증폭기를 첫 단에 두었다. 또한 동작 속도를 높이기 위하여 고속의 전치증폭기와 래치를 순차적으로 구성하였다. 두 시험 소자(DUT) 간 출력 신호 차이를 검출함에 있어, 공통 신호와 차동 신호 차이를 모두 감지하기 위하여 차동차이 증폭기(DDA)를 사용하였다. 이 비교기는 $0.18{\mu}m$ BCDMOS 공정을 사용하여 칩으로 구현되었으며, 5mV의 신호 차이를, 800 MHz의 신호까지 비교가 가능하다. 구현된 칩 면적은 $620{\mu}m{\times}830{\mu}m$이다.

• 한국컴퓨터정보학회논문지
• /
• 제24권2호
• /
• pp.57-66
• /
• 2019

This paper compared the performance with an overview of channel equalization techniques used in high-speed serial transceivers, including the homogeneous architecture and associated components for the GHz interconnect of backplane and cable channels. It also used the MATLAB tool to present system analysis and simulation results for continuous time equivalent structures. In the case of conventional continuous equalization, high frequency deficits occur due to the use of a comparator that is difficult to implement as well as the low speed limit. In this paper, the channel equalization technique based on the power spectrum analysis of clocks was used to compensate for the frequency loss, and the application of the TX+Channel and TX+Equalizer filters enabled the measurement of attenuation and equivalence without comparators. The application of blender and band-pass filters at high speeds also showed significant effectiveness.