• International Journal of Aeronautical and Space Sciences
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• 제7권1호
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• pp.91-98
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• 2006

The thermomechanical behaviors of SMA thin film actuator and their application are investigated. The numerical algorithm of the 2-D SMA thermomechanical constitutive equation is developed and implemented into the ABAQUS finite element program by using the user defined material (UMAT) subroutine. To verify the numerical algorithm of SMAs, the results are compared with experimental data. For the application of SMA thin film actuator, the methodology to maintain the precise configuration of inflatable membrane structure is demonstrated.

• 한국산학기술학회논문지
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• 제5권5호
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• pp.389-394
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• 2004

이 논문에서는 플래시 메모리의 특성에 따른 메모리 재활용 방법론을 제안하여 비용을 감소시키면서 동시에 성능의 감소를 방지하는 목적을 만족시키고자 한다. 새로운 방법론은 재활용 대상 메모리 세그먼트 공간을 K 개의 하부 공간으로 분할하여 전체 검색을 대신 부분 검색을 실행하여 비용의 최소화를 추구한다. 아울러, 새로운 메모리 공간 배정 결정 시 전체 플래시 메모리 공간의 균등 소거에 대한 개선책을 제안한다. 제안된 방법론의 최적화를 위하여 하부 공간 분할 크기를 실험을 통해 취득 하였다. 실험적 자료는 제안된 방법론이 기존의 방법론과 비교하였을 교 비용은 감소하고 성능은 개선되는 것을 예시한다. 또한, 실험을 통해 메모리 공간 배정이 메모리 공간의 균등 소거에 많은 영향을 미친다는 사실을 확인할 수 있다.

• 한국콘텐츠학회논문지
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• 제8권5호
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• pp.72-81
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• 2008

고성능 DSP는 보통 캐쉬와 내부 메모리를 지원한다. 이러한 고성능 DSP에 멀티미디어 스트림 응용을 최적화하여 구현하고자 하는 경우에는, DSP 가 지원하는 캐쉬와 내부 메모리를 효율적으로 잘 활용하여야 한다. 본 논문에서는 2단계 레벨 캐쉬 구조 및 내부 메모리 구성을 지원하는 고성능 DSP인 TMS320C6000 시리즈에 대해 동영상 인코더와 같은 멀티미디어 스트림 처리 응용을 최적으로 구현하기 위해서 필요한 캐쉬 성능 분석, 내부 메모리 구성 및 배치에 따른 성능 분석과 개선 방안에 대해 연구하였다. 분석 및 실험 결과, L2 메모리의 경우, 이중 집합연관 캐쉬로 구성하고, 남은 메모리는 내부 메모리로 구성하는 것이 수행 시간 성능 개선에 효과적임을 확인하였다. 또한, L1P 캐쉬의 경우는 자주 호출되고 시간이 많이 소요되는 루틴들을 연속적으로 내부 메모리에 배치하는 것이 L1P 캐쉬의 히트 율을 개선하며, L1D 캐쉬의 경우는 사용하는 데이터의 크기를 조절하므로 써 쉽게 히트 율을 개선할 수 있다는 것을 밝혔다. 본 논문의 연구 결과는 고성능 DSP 에 멀티미디어 스트림 처리 응용을 최적화로 구현하는데 도움을 줄 것으로 기대한다.

• 한국실내디자인학회논문집
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• 제22권4호
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• pp.70-77
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• 2013

This study has analysed the composition elements in a cafe space where visual transfer-elements are filled and the perceptual characteristics of facade designs with the purpose of drawing any important elements to advertisement and their related items for uniqueness of designs. For the analysis of the perception process shown in the consecutive situations of observing and visiting cafes, the cafe facade was grouped and stereotyped for the analysis of perceptual characteristics and significant composition elements for better designing of cafes through survey with representative facades as subjects. The conclusions from this study are the followings. First, for the uniqueness specific to cafes to be integrated into facade, memory was chosen first as the most significant advertisement factor followed by interest as with male and attention as with female. The memory has much to do with furniture and finishing material of Clause (4), Chapter 4.1 and the types having effects on perception of Clause (1) and the atmosphere having effect on that of Clause (2) were found to be major factors to attention and interest. Second, it was found out that women preferred horizontally stable partition and men clearly divided facades. The factor of shape was observed first among the constituents of facade followed by color. There was no difference with 'shape' between men and women and color was found to be a space constituent having a lot of effects on women. Third, the memory of experience from visiting a cafe was very likely to offer the motivation of visiting it again, on which furniture had the most effect followed by finishing material and color. Such elevation elements as facade and logo were found not to have effect on the memory or the re-visit. Any intention of visiting again seemed to be influenced by such comprehensive images as atmosphere rather than by any concrete facade, furniture, or appliance. From the above viewpoint, facade design should have any uniqueness or impressive feature as well as the effect of making passers-by drop in and attracting them into the shop. The analysis of attributes of facade constituents revealed that the abstract images in addition to the configuration of facade had much to do with interest or behavior.

• 전자공학회논문지A
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• 제32A권5호
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• pp.737-748
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• 1995

In this paper, we studyed the variables in the design of multichip memory modules with 4M$\times$1bit DRAM chips to construct high capacity and high speed memory modules. The configuration of the module was 8 bit, 16 bit, and 32 bit DRAM modules with employing 0.6 W, 70 nsec 4M$\times$1 bit DRAM chips. We optimized routing area and wiring density by performing the routing experiment with the variables of the chip allocation, module I/O terminal, the number of wiring, and the number of mounting side of the chips. The multichip module was designed to be able to accept MCM-L techiques and low cost PCB materials. The module routing experiment showed that it was an efficient way to align chip I/O terminals and module I/O terminals in parallel when mounting bare chips, and in perpendicular when mounting packaged chips, to set module I/O terminals in two sides, to use double sided substrates, and to allocate chips in a row. The efficient number of wiring layer was 4 layers when designing single sided bare chip mounting modules and 6 layers when constructing double sided bare chip mounting modules whereas the number of wiring layer was 3 layers when using single sided packaged chip mounting substrates and 5 layers when constructing double sided packaged chip mounting substrates. The most efficient configuration was to mount bare chips on doubled substrates and also to increase the number of mounting chips. The fabrication of memory multichip module showed that the modules with bare chips can be reduced to a half in volume and one third in weight comparing to the module with packaged chips. The signal propagation delay time on module substrate was reduced to 0.5-1 nsec.

• 한국통신학회논문지
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• 제21권1호
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• pp.224-240
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• 1996

It is common sense for at least one or more levels of cache memory to be used in these day's computer systems. In this paper, the impact of the internal cache memory organization on the performance of the computer is investigated by using a simulator program, which is wirtten by authors and run on SUN SPARC workstation, with several real execution, with several real execution trace files. 280 cache organizations have been simulated using n-way set associative mapping and LRU(Least Recently Used) replacement algorithm with write allocation policy. As a result, 16-way setassociative cache is the best configuration, and when we select 256KB cache memory and 64 byte line size, the bus traffic ratio was decreased compared to that of the noncache system so that a single bus could support almost 7 processors without any delay and degradationof high ratio(hit ratio was 99.21%). The smaller the line size we choose, the little lower hit ratio we can get, but the more processors can be supported by a single bus(maximum 18 processors). Therefore, using a proper cache memory organization can make a single bus structure be able to support multiple processors without any performance degradation.

• 한국항공우주학회지
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• 제38권4호
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• pp.389-394
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• 2010

본 연구에서는 과학기술위성 2호와 비교 했을 때 고속의 데이터를 처리하고 대용량의 메모리를 관리해야하는 요구사항을 만족하기 위한 과학기술위성 3호 대용량 메모리 유닛의 설계 내용에 대해서 나타내었다. 이러한 요구사항을 만족하기 위해서, 두 개의 탑재체에서 각각 최대 100Mbps로 수신되는 데이터와 32Gb의 대용량 메모리를 처리하고 관리하는 역할을 FPGA가 직접 담당 하도록 설계하였다. 사용된 FPGA는 동작 속도가 빠르고 게이트 수가 많은 SRAM 기반의 Xilinx FPGA로써 우주 환경에서의 SEU를 극복하기 위해서 TMR 기법과 스크러빙 기법을 적용하고자 한다.

• 한국전기전자재료학회논문지
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• 제36권1호
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• pp.23-28
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• 2023

This paper demonstrates a novel NAND flash memory structure and annealing configuration including through-silicon via (TSV) inside the silicon substrate to improve annealing efficiency using an electro-thermal annealing (ETA) technique. Compared with the conventional ETA which utilizes WL-to-WL current flow, the proposed annealing method has a higher annealing temperature as well as more uniform heat distribution, because of thermal isolation on the silicon substrate. In addition, it was found that the annealing temperature is related to the electrical and thermal conductivity of the TSV materials. As a result, it is possible to improve the reliability of NAND flash memory. All the results are discussed based on 3-dimensional (3-D) simulations with the aid of the COMSOL simulator.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 춘계학술대회 논문집 센서 박막재료 반도체재료 기술교육
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• pp.107-110
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• 2002

The optical memory devices of BST thin films to composite $(Ba_{0.7}\;Sr_{0.3})TiO_{3}$ using sol-gel method were fabricated by changing of the depositing layer number on $Pt/Ti/SiO_{2}/Si$ substrate. The structural properties of optical memory devices to be ferroelectric was investigated by fractal analysis and 3-dimension image processing. The thickness of BST thin films at each coating numbers 3, 4 and 5 times was $2500[\AA]$, $3500[\AA]$ and $3800[\AA]$. BST thin films exhibited the most pronounced grain growth. The surface morphology image was roughness with coating numbers. The thin films increasing with coating numbers shows a more textured and complex configuration.

• Structural Engineering and Mechanics
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• 제53권5호
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• pp.1031-1049
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• 2015

This paper highlights the role of innovative vibration control system based on two promising properties in a parallel configuration. Hybrid device consists of two main components; recentering wires of shape memory alloy (SMA) and steel pipe section as an energy dissipater element. This approach concentrates damage in the steel pipe and prevents the main structural members from yielding. By regulation of the main adjustable design parameter, an optimum performance of the device is obtained. The effectiveness of the device in passive control of structures is evaluated through nonlinear time history analyses of a five-story steel frame with and without the hybrid device. Comparing the results proves that the hybrid device has a considerable potential to mitigate the residual drift ratio, peak absolute acceleration and peak interstory drift of the structure.