• Progress in Superconductivity
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• v.5 no.1
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• pp.21-25
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• 2003

We have designed and simulated an 1-bit ALU (Arithmetic Logic Unit) by using a half adder. An ALU is the part of a computer processor that carries out arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We constructed an 1-bit ALU by using only one half adder and three control switches. We designed the control switches in two ways, dc switch and NDRO (Non Destructive Read Out) switch. We used dc switches because they were simple to use. NDRO pulse switches were used because they can be easily controlled by control signals of SET and RESET and show fast response time. The simulation results showed that designed circuits operate correctly and the circuit minimum margins were ＋/-27%. In this work, we used simulation tools of XIC and WRSPICE. The circuit layouts were also performed. The circuits are being fabricated.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.164-166
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• 2005

In this paper, using ranks of co-occurrence frequency about indices in neighboring pixels, we introduce a new re-indexing scheme for efficiency of index color image lossless compression. The proposed method is suitable for arithmetic coding because it has skewed distributions of small variance. Experimental results proved that the proposed method reduces the bit rates than other coding schemes, more specifically 15%, 54% and 12% for LZW algorithm of GIF, the plain arithmetic coding method and Zeng's scheme.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.8 no.12
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• pp.127-138
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• 1985

There are several methods which have been presented up to now in solving the simultaneous linear equations by computer. They are Gaussian Elimination Method, Gauss-Jordan Method, Inverse matrix Method and Gauss-Seidel iterative Method. This paper is not only discussed in their mechanisms compared with their algorithms, depicted flow charts, but also calculated the numbers of arithmetic operations and comparisons in order to criticize their availability. Inverse Matrix Method among em is founded out the smallest in the number of arithmetic operation, but is not the shortest operation time. This paper also indicates the many problems in using these methods and propose the new method which is able to applicate to even small or middle size computers.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.3
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• pp.636-644
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• 2015

This research aims to suggest methods to improve object tracking performance by combining CAM shift algorithm with 8-way search window, and reduce arithmetic operation by reducing the number of frame used for tracking. CAM shift has its adverse effect in tracking methods using signature color or having difficulty in tracking rapidly moving object. To resolve this, moving search window of CAM shift makes it possible to more accurately track high-speed moving object after finding object by conducting 8-way search by using information at a final successful timing point from a timing point missing tracking object. Moreover, hardware development led to increased unnecessary arithmetic operation by increasing the number of frame produced per second, which indicates efficiency can be enhanced by reducing the number of frame used in tracking to reduce unnecessary arithmetic operation.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.8
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• pp.453-464
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• 2004

In order to solve the well-known drawback of reduced flexibility that is associate with ASIC implementations, this paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for field programmable gate arrays (FPGAs) implementations of elliptic curve cryptographic processor. The proposed arithmetic unit is based on the binary extended GCD algorithm and the MSB-first multiplication scheme, and designed as systolic architecture to remove global signals broadcasting. The proposed architecture can perform both division and multiplication in GF(2$^{m}$ ). In other word, when input data come in continuously, it produces division results at a rate of one per m clock cycles after an initial delay of 5m-2 in division mode and multiplication results at a rate of one per m clock cycles after an initial delay of 3m in multiplication mode respectively. Analysis shows that while previously proposed dividers have area complexity of Ο(m$^2$) or Ο(mㆍ(log$_2$$^{m}$ )), the Proposed architecture has area complexity of Ο(m), In addition, the proposed architecture has significantly less computational delay time compared with the divider which has area complexity of Ο(mㆍ(log$_2$$^{m}$ )). FPGA implementation results of the proposed arithmetic unit, in which Altera's EP2A70F1508C-7 was used as the target device, show that it ran at maximum 121MHz and utilized 52% of the chip area in GF(2$^{571}$ ). Therefore, when elliptic curve cryptographic processor is implemented on FPGAs, the proposed arithmetic unit is well suited for both division and multiplication circuit.

• 제어로봇시스템학회:학술대회논문집
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• 1991.10b
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• pp.1617-1622
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• 1991

Plane sweep is a general method in computational geometry. There are many efficient theoretical algorithms designed using plane sweep technique. However, their practical implementations are still suffering from the topological inconsistencies resulting from the numerical errors in geometric computations with finite-precision arithmetic. In this paper, we suggest new implementation techniques for the plane sweep algorithms to resolve the topological inconsistencies and construct the planar object boundaries from given input curve segments.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.10
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• pp.520-529
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• 2001

Carry-save-adder(CSA) is one of the most effective operation cells in implementing an arithmetic hardware with high performace and small circuit area. An fundamental drawback of the existing CAS applications is that the applications are limited to the local parts of arithmetic circuit that are directly converted to additions. To resolve the limitation, we propose a set of new CSA transformation techniques: optimizing arithmetics with multiplexors, optimizing arithmetics in multiple designs, and optimizing arithmetics with multiplications. We then design a new CSA transformation algorithm which integrates the proposed techniques, so that we are able to utilize CSAs more globally. An extensive experimentation for practical designs are provided to show the effectiveness of our proposed algorithm over the conventional CSA techniques.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1891-1898
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• 2013

To efficiently execute 3D graphic APIs, such as OpenGL and Direct3D, special purpose arithmetic unit(SFU) which supports floating-point sine, cosine, reciprocal, inverse square root, base-two exponential, and logarithmic operations is designed. The SFU uses second order minimax approximation method and lookup table method to satisfy both error less than 2 ulp(unit in the last place) and high speed operation. The designed circuit has about 2.3-ns delay time under 65nm CMOS standard cell library and consists of about 23,300 gates. Due to its maximum performance of 400 MFLOPS and high accuracy, it can be efficiently applicable to mobile 3D graphics application.

• Journal of IKEEE
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• v.22 no.3
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• pp.805-809
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• 2018

In this paper, we analyze the change of accuracy when fixed point arithmetic is used instead of floating point arithmetic in binary weight network(BWN). We observed the change of accuracy by varying total bit size and fraction bit size. If the integer part is not changed after fixed point approximation, there is no significant decrease in accuracy compared to the floating-point operation. When overflow occurs in the integer part, the approximation to the maximum or minimum of the fixed point representation minimizes the decrease in accuracy. The results of this paper can be applied to the minimization of memory and hardware resource requirement in the implementation of FPGA-based BWN accelerator.

• Progress in Superconductivity
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• v.8 no.2
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• pp.181-185
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• 2007

For more than two decades Nb trilayer ($Nb/Al_2O_3/Nb$) process has been serving as the most stable fabrication process of the Josephson junction integrated circuits. Fast development of semiconductor fabrication technology has been possible with the recent advancement of the fabrication equipments. In this work, we took an advantage of advanced fabrication equipments in developing a superconducting Arithmetic Logic Unit (ALU) by using Nb trilayers. The ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We used DC magnetron sputtering technique for metal depositions and RF sputtering technique for $SiO_2$ depositions. Various dry etching techniques were used to define the Josephson junction areas and film pattering processes. Our Nb films were stress free and showed the $T{_c}'s$ of about 9 K. To enhance the step coverage of Nb films we used reverse bias powered DC magnetron sputtering technique. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. Our 1-bit ALU operated correctly at up to 40 GHz clock frequency, and the 4-bit ALU operated at up to 5 GHz clock frequency.