• 디지털산업정보학회논문지
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• 제18권1호
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• pp.1-9
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• 2022

Galois field arithmetic is important in error correcting codes and public-key cryptography schemes. Hardware realization of these schemes requires an efficient implementation of Galois field arithmetic operations. Multiplication is the main finite field operation and designing efficient multiplier can clearly affect the performance of compute-intensive applications. Diverse algorithms and hardware architectures are presented in the literature for hardware realization of Galois field multiplication to acquire a reduction in time and area. This paper presents a low complexity semi-systolic multiplier to facilitate parallel processing by partitioning Montgomery modular multiplication (MMM) into two independent and identical units and two-level systolic computation scheme. Analytical results indicate that the proposed multiplier achieves lower area-time (AT) complexity compared to related multipliers. Moreover, the proposed method has regularity, concurrency, and modularity, and thus is well suited for VLSI implementation. It can be applied as a core circuit for multiplication and division/exponentiation.

• 디지털산업정보학회논문지
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• 제9권1호
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• pp.95-102
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• 2013

This paper covers nulling algorithm. In this algorithm, we assume that nulling points are already known. In general, nulling algorithm using matrix equation was utilized. But, this algorithm is pointed out that computational complexity is disadvantage. So, we choose gradient method to reduce the computational complexity. In order to further reduce the computational complexity, we propose approximate gradient method using characteristic of trigonometric functions. The proposed method has same performance compared with conventional method while having half the amount of computation when the number of antenna and nulling point are 20 and 1, respectively. In addition, we could virtually eliminate the trigonometric functions arithmetic. Trigonometric functions arithmetic cause a big problem in actual implementation like FPGA processor(Field Programmable gate array). By utilizing the above algorithm in a multi-cell environment, beamforming gain can be obtained and interference can be reduced at same time. By the above results, the algorithm can show excellent performance in the cell boundary.

• Journal of applied mathematics & informatics
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• 제20권1_2호
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• pp.637-645
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• 2006

An adaptive algorithm for reducing the hardware complexity is presented. This paper proposes a simplified LMS algorithm for the adaptive system and analyzes its convergence characteristics mathematically. An objective of the proposed algorithm is to reduce the hardware complexity. In order to test the performances, it is applied to the echo canceller, and a program is described. The results from simulations show that the echo canceller adopting the proposed algorithm achieves almost the same performances as one adopting the NLMS algorithm. If an echo canceller is implemented with this algorithm, its computation quantities are reduced to the half as many as the one that is implemented with the LMS algorithm, without so much degradation of performances.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제12권12호
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• pp.5723-5743
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• 2018

The evolving internet-based services demand high-speed data transmission in conjunction with scalability. The next generation optical network has to exploit artificial intelligence and cognitive techniques to cope with the emerging requirements. This work proposes a novel way to solve the dynamic provisioning problem in optical network. The provisioning in optical network involves the computation of routes and the reservation of wavelenghs (Routing and Wavelength assignment-RWA). This is an extensively studied multi-objective optimization problem and its complexity is known to be NP-Complete. As the exact algorithms incurs more running time, the heuristic based approaches have been widely preferred to solve this problem. Recently the software-defined networking has impacted the way the optical pipes are configured and monitored. This work proposes the dynamic selection of path computation algorithms in response to the changing service requirements and network scenarios. A software-defined controller mechanism with a novel packet matching feature was proposed to dynamically match the traffic demands with the appropriate algorithm. A software-defined controller with Path Computation Element-PCE was created in the ONOS tool. A simulation study was performed with the case study of dynamic path establishment in ONOS-Open Network Operating System based software defined controller environment. A java based NOX controller was configured with a parent path computation element. The child path computation elements were configured with different path computation algorithms under the control of the parent path computation element. The use case of dynamic bulk path creation was considered. The algorithm selection method is compared with the existing single algorithm based method and the results are analyzed.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
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• pp.20-22
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• 2007

The H.264/AVC standard developed by the joint Video Team (JVT) provides better coding efficiency than previous standards. The new emerging H.264/AVC employs variable block size motion estimation using multiple reference frame with 1/4-pel MV(Motion Vector) accuracy. These techniques are a important feature to accomplish higher coding efficiency. However, these techniques are increased overall computational complexity. To overcome this problem, this paper proposes advanced fast mode decision suited for variable block size by classifying inter mode based on Rate Distortion Optimization(RDO) technique. Proposed algorithm is going to use to implement H/W structure for fast mode decision. The experimental results shows that the proposed algorithm provides significant reduction computational complexity without any noticeable coding loss and additional computation. Entire computational complexity is decreased about 30%.

• 전기학회논문지
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• 제65권3호
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• pp.463-468
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• 2016

The overall performance of multiuser systems significantly depends on how effectively and fairly manage resources shared by them. The efficient resource management strategies are even more important for multimedia users since multimedia data is delay-sensitive and massive. In this paper, we focus on resource allocation based on a game-theoretic approach, referred to as Nash bargaining solution (NBS), to provide a quality of service (QoS) guarantee for each user. While the NBS has been known as a fair and optimal resource management strategy, it is challenging to find the NBS efficiently due to the computationally-intensive task. In order to reduce the computation requirements for NBS, we propose an approach that requires significantly low complexity even when networks consist of a large number of users and a large amount of resources. The proposed approach linearizes utility functions of each user and formulates the problem of finding NBS as a convex optimization, leading to nearly-optimal solution with significantly reduced computation complexity. Simulation results confirm the effectiveness of the proposed approach.

• Journal of Power Electronics
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• 제19권6호
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• pp.1429-1439
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• 2019

Buck-Boost LLC (BBLLC) converters based on a PWM + phase control strategy are good candidates for high efficiency, high power density and wide input range applications. Nevertheless, they suffer from large computational complexity when it comes to calculating the optimal phase for ZVS of all the switches. In this paper, a method is proposed for a microcontroller unit (MCU) to calculate the optimal phase quickly and accurately. Firstly, a 2-D lookup table of the phase is established with an index of the input voltage and output current. Then, a bilinear interpolation method is applied to improve the accuracy. Meanwhile, simplification of the phase equation is presented to reduce the computational complexity. When compared with conventional curve-fitting and LUT methods, the proposed method makes the best tradeoff among the accuracy of the optimal phase, the computation time and the memory consumption of the MCU. Finally, A 350V-420V input, 24V/30A output experimental prototype is built to verify the proposed method. The efficiency can be improved by 1% when compared with the LUT method, and the computation time can be reduced by 13.5% when compared with the curve-fitting method.

• Journal of information and communication convergence engineering
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• 제7권2호
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• pp.193-198
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• 2009

The H.264/ AVC video coding standard supports the intra prediction with various block sizes for luma component and a 8x8 block size for chroma components. This new feature of H.264/AVC offers a considerably higher improvement in coding efficiency compared to previous compression standards. In order to achieve this, H.264/AVC uses the Rate-distortion optimization (RDO) technique to select the best intra prediction mode for each block size, and it brings about the drastic increase of the computation complexity of H.264 encoder. In this paper, a fast block size decision algorithm is proposed to reduce the computation complexity of the intra prediction in H.264/AVC. The proposed algorithm computes the smoothness based on AC and DC coefficient energy for macroblocks and compares with the nonparametric criteria which is determined by considering information on neighbor blocks already reconstructed, so that deciding the best probable block size for the intra prediction. Also, the use of non-parametric criteria makes the performance of intra-coding not be dependent on types of video sequences. The experimental results show that the proposed algorithm is able to reduce up to 30% of the whole encoding time with a negligible loss in PSNR and bitrates and provides the stable performance regardless types of video sequences.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권1호
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• pp.44-57
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• 2016

Rectification is used as a preprocessing to reduce the computation complexity of disparity estimation. However, rectification also requires a complex computation. To minimize the computing complexity, rectification using a lookup-table (R-LUT) has been introduced. However, since, the R-LUT consumes large amount of memory, rectification with compressed LUT (R-CLUT) has been introduced. However, the more we reduce the memory consumption, the more we need decoding overhead. Therefore, we need to attain an acceptable trade-off between the size of LUT and decoding overhead. In this paper, we present such a trade-off by adaptively combining simple coding methods, such as differential coding, modified run-length coding (MRLE), and Huffman coding. Differential coding is applied to transform coordinate data into a differential form in order to further improve the coding efficiency along with Huffman coding for better stability and MRLE for better performance. Our experimental results verified that our coding scheme yields high performance with maintaining robustness. Our method showed about ranging from 1 % to 16 % lower average inverse of compression ratio than the existing methods. Moreover, we maintained low latency with tolerable hardware overhead for real-time implementation.

• 대한임베디드공학회논문지
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• 제14권6호
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• pp.313-319
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• 2019

Finite field operations have played an important role in error correcting codes and cryptosystems. Recently, the necessity of efficient computation processing is increasing for security in cyber physics systems. Therefore, efficient implementation of finite field arithmetics is more urgently needed. These operations include addition, multiplication, division and inversion. Addition is very simple and can be implemented with XOR operation. The others are somewhat more complicated than addition. Among these operations, multiplication is the most important, since time-consuming operations, such as exponentiation, division, and computing multiplicative inverse, can be performed through iterative multiplications. In this paper, we propose a multiplexer based parallel computation algorithm that performs Montgomery multiplication over finite field using redundant basis. Then we propose an efficient multiplexer based semi-systolic multiplier over finite field using redundant basis. The proposed multiplier has less area-time (AT) complexity than related multipliers. In detail, the AT complexity of the proposed multiplier is improved by approximately 19% and 65% compared to the multipliers of Kim-Han and Choi-Lee, respectively. Therefore, our multiplier is suitable for VLSI implementation and can be easily applied as the basic building block for various applications.