• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(1)
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• pp.101-104
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• 2002

In this parer, a novel architecture for Home gateway is Proposed. In home network system, there exist many different kinds of data types, like audio, video, and control information. And the communication is over multiple networks, like bluetooth, wireless LAN, USB, IEEE1394, and Power Line Communication (PLC). The hardware architecture of the Home gateway presented in this paper is based on ISO/1EC JTC 1/sc 2S/WG 1(1,2). The architecture proposed in this paper takes into account the characteristics of home network environment, so the Packets in the home network system can be processed very efficiently.

• 시스템엔지니어링학술지
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• 제11권1호
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• pp.25-31
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• 2015

Under the relevant regulations, it is required to develop a system architecture for the research and development of the information and communication infra system ; however, the national defense architecture development guides and MND-AF, which provide the instructions on the development and utilization of a system architecture, are still limited to the ITA level and merely providing the guidelines for developing the information system centric architecture. Thus, it is evident that we need a suitable architecture development methodology that corresponds to the growing needs for the communication infra system architecture, as well as the general weapon system architecture. Improving a meta-model is the core of improving a architecture framework. It determines a contents of a architecture and it influences a efficiency and a effectiveness of a architecture. The meta-model of the architecture framework must reflect concerns of various stakeholders and provide a traceability among them. Also, it should be easy to develop and use the architecture by securing the feasibility of the logical relationships and eliminating the duplication of the data inside the architecture. It is implemented through the development of the data-centric architecture and achieved through the "Fit-for-purpose" concept.

• 한국디지털건축인테리어학회논문집
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• 제8권2호
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• pp.39-46
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• 2008

Current architecture can receive support of and command various ways of expression by more advanced technology of the present time, this means the formation of changeable external design of building, and has the tendency to be interactive non-rheological shape. Accordingly surface of building is decorated not only by the basic function and the expression of information, but also by complex narrative image structure or text, so far as recognizes human as the subject of communication, and is trying the artistic expression interacting with the general public. In various expressive tendency of current architecture surface design, such an approach from a view of an interactive art trying the communication between architecture, art, and human has the meaning of suggesting the direction of directing emotional architecture giving a present to the morderners who are growing more and more an earnest desire for experiencing culture and art in their daily life.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2014년도 추계학술발표대회
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• pp.171-172
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• 2014

This paper proposes a SDN based Proxy Mobile IPv6 (PMIPv6) architecture for heterogeneous vehicular networks (SDN-VANET), to provide the continuity of service during the horizontal handovers and to reduce the delay during vertical and horizontal handovers. SDN-VANET mainly relies on DSRC road side units (RSUs) for V2I communication and to overcome the coverage problem SDN-VANET performs the vertical handover between DSRC and LTE/UMTS. To date there is no standard to perform network layer vertical handovers. Therefore the proposed SDN-VANET architecture also doesn't provide any mechanism for vertical network layer handovers, but solves the horizontal network layer handovers in DSRC or LTE/UMTS through introducing PMIPv6 in the architecture.

• International Journal of Computer Science & Network Security
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• 제22권11호
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• pp.87-92
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• 2022

Today the system of higher education needs significant reforms. Intellectualization of the educational process in HEIs aims to improve the quality of educational services. Intellectual information technologies are information technologies that help a person to accelerate the analysis of the political, economic, social, and technical situation, as well as the synthesis of management decisions. The basis for their mastery is information and communication technologies. The purpose of the research work is to identify the relationship between the introduction of information and communication technologies and the increase in the level of intellectualization of higher education. The article substantiates the expediency of introducing information and communication technologies in order to improve the intellectualization of the educational process in higher education. An empirical study of the variables that characterize the level of intellectualization of higher education through the proposed techniques has been conducted. The tendencies characteristic of pedagogical conditions of implementation of information and communication model in the educational process were revealed. It is proved that the level of intellectualization of higher education depends on the implemented pedagogical conditions. The effectiveness of the proposed information and communication model is also confirmed. Given the data obtained during the study and the low constraints that may affect the results of further research on this issue should focus on the study of other variables that characterize the state of intellectualization of the educational process.

• ETRI Journal
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• 제29권6호
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• pp.820-822
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• 2007

ARIA and the Advanced Encryption Standard (AES) are next generation standard block cipher algorithms of Korea and the US, respectively. This letter presents an area-efficient unified hardware architecture of ARIA and AES. Both algorithms have 128-bit substitution permutation network (SPN) structures, and their substitution and permutation layers could be efficiently merged. Therefore, we propose a 128-bit processor architecture with resource sharing, which is capable of processing ARIA and AES. This is the first architecture which supports both algorithms. Furthermore, it requires only 19,056 logic gates and encrypts data at 720 Mbps and 1,047 Mbps for ARIA and AES, respectively.

• 한국컴퓨터산업학회논문지
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• 제2권9호
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• pp.1239-1244
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• 2001

클러스터시스템의 표준 고속통신구조로서 Virtual Interface Architecture (VIA)가 일반적으로 제안되어진다. 그러나 현재 VIA 및 Virtual Interface Provider Library (VIPL)의 사양은 POSIX의 정해진 Fork 나 시그널 기능에 응답하는 규정이 없거나, 디스크립터가 잘못 규정되어지는 등, Windows OS와 Intel 아키텍처의 CPU에만 적합하도록 되어 있는 부분이 있다. 본 논문에서는 OS와 CPU 아키텍처의 중립적인 시각에서 VIA 및 VIPL의 문제점을 명확화하고, 다른 OS나 CPU에의 상용화를 목적으로 하는 해결 방식을 제안한다.

• 한국시뮬레이션학회:학술대회논문집
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• 한국시뮬레이션학회 2005년도 춘계학술대회 논문집
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• pp.1-4
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• 2005

Information communication environment integrates communication, broadcasting and internet, and Digital Convergence service emerges in result. Thus, the effective routers are needed so that they can transmit a huge number of data to core internet through appropriate base center. Therefore, the network guaranteeing QoS in transport layer supports interoperability with different wireless networks. So as to users receive necessary information anywhere seamlessly, the network architecture focuses on packet transmission and it is efficient for the control layer switches and controls packets between different networks. Since individual users take advantage of different services and data, the effective router architecture must be designed. Hence in this paper we design monitoring technique to solve security problem and to support premium service to ultimate users. Thereafter, we run opnet simulation and show the improvement of proposed router architecture.

• Journal of Electrical Engineering and information Science
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• 제1권2호
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• pp.15-26
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• 1996

MPAs(Massively Parallel Architectures) should address two fundamental issues for scalability: synchronization and communication latency. Dataflow architecture faces problems of excessive synchronization overhead and inefficient execution of sequential programs while they offer the ability to exploit massive parallelism inherent in programs. In contrast, MPAs based on von Neumann computational model may suffer from inefficient synchronization mechanism and communication latency. DAVRID (DAtaflow/Von Neumann RISC hybrID) is a massively parallel multithreaded architecture which takes advantages of von Neumann and dataflow models. It has good single thread performance as well as tolerates synchronization and communication latency. In this paper, we describe the DAVRID architecture in detail and evaluate its performance through simulation runs over several benchmarks.

• 대한전자공학회논문지SD
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• 제41권12호
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• pp.67-74
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• 2004

AES는 인터넷 프로토콜의 대칭키 보안 알고리즘으로 널리 사용된다. 무선 내장형 시스템들이 점점 더 전통적인 유선 네트워크 프로토콜을 많이 사용하고 있으므로 이들 무선 내장형 시스템을 위한 저비용 AES 알고리즘 구현은 매우 중요하다. 가장 기본적인 AES 아키텍처는 키 스케줄을 포함하여 20개의 S-box를 사용하는 하나의 cipher 라운드로 구성되어 있다. 암호화는 동일한 라운드를 반복하여 완료된다. 근래에 이 방법의 구현 비용을 더욱 줄이기 위하여 오직 8개의 S-box만 사용하는 folded architecture가 제안되었다. 본 논문에서는 folded architecture를 이용하여 무선 통신 기술을 위한 저비용 AES 구현 구조에 대하여 연구한다. 먼저 folded architecture를 개선하여 16 바이트의 추가적인 상태 메모리 사용을 줄였다. 구현 비용을 더욱 줄이기 위하여 데이터 암호화에 하나의 S-box만 사용하는 single byte architecture를 구현하였다. Single byte architecture는 암호화에 352 클록이 소요된다. FPGA 구현 시 최대 동작 주파수는 40MHz에 도달하였다. 따라서 암호화 속도는 13Mbps 이상으로 3G 무선통신에 충분하다.