• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.1
• /
• pp.28-37
• /
• 2010

In this paper, the IC (Integrated Circuit) for multi-channel asynchronous communication was designed by using FPGA and VHDL language. The existing chips for asynchronous communication that has been used commercially are composed of one to two channels. Therefore, when communication system with two channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 asynchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 256 bytes respectively and consequently high speed communication became possible. To detect errors between communications, it was designed with digital filter and check-sum logic and channel MUX logic so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. It was composed and simulated logic of VHDL described by using Cyclone II Series EP2C35F672C8 and QuartusII V8.1 of ALTERA company. In order to show the performance of designed IC, the test was conducted successfully in QuartusII simulation and experiment and the excellency was compared with TL16C550A of TI (Texas Instrument) company and ATmegal28 general-purpose micro controller of ATMEL company that are used widely as chips for asynchronous communication.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.13 no.4
• /
• pp.85-98
• /
• 2003

Computational power of IC chip is improved day after day producing IC chips holding co-processor continuously. Also a lot of wireless terminals which IC chip embedded in are produced in order to provide simple and various services in the wireless terminal market. However it is difficult to apply the key distribution protocol under wired communication environment to wireless communication environment. Because the computational power of co-processor embedded in IC chip under wireless communication environment is less than that under wired communication environment. In this paper, we propose the hey distribution protocol appropriate for wireless communication environment which diminishes the computational burden of server and client by using co-processor that performs cryptographic operations and makes up for the restrictive computational power of terminal. And our proposal is satisfied with the security requirements that are not provided in existing key distribution protocol.

• Journal of the Semiconductor & Display Technology
• /
• v.10 no.4
• /
• pp.7-13
• /
• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

• Journal of the Semiconductor & Display Technology
• /
• v.10 no.3
• /
• pp.1-6
• /
• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2004.05a
• /
• pp.797-800
• /
• 2004

FED(Field Emission Display)는 CRT(Cathode Ray Tube)의 화질과 LCD(Liquid Crystal Display)와 같은 FPD(Flat Panel Display)의 경량, 박형의 장점을 만족시키는 차세대 Display 소자로서 주목을 받고 있다. 본 논문은 저항열을 이용하여 256 Gray-Scale Level을 출력하는 8 비트 FED Data Driver IC 설계에 관한 것이다. 즉, 저항열과 D/A 변환기를 통하여 디지털 입력 데이터에 따른 아날로그 출력 데이터를 갖는 FED 용 Data Driver IC이다. 본 논문에서 설계된 Driver IC는 집적도를 높여 Output Channel 수를 증가시키는 것을 목표로, 하이닉스 0.6um High Voltage 공정을 사용하였으며, 8 비트 RGB 데이터 입력과 40V 구동전압에서 동작하도록 설계하였다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.24 no.6
• /
• pp.633-643
• /
• 2013

GDS format files, as well as layout of the chip are noticeably needed so as to analyze the PDN (Power Delivery Network) inside of IC; however, commercial IC in the market has not supported design information which is layout of IC. Within this, in terms of IC having on-chip PDN, characteristic of inside PDN of the chip is a core parameter to predict generated noise from power/ground planes. Consequently, there is a need to scrutinize extraction method for unknown PDN of the chip in this paper. To extract PDN of the chip without IC circuit information, the de-embedding test vehicle is fabricated based on IEC62014-3. Further more, the extracted inside PDN of chip from de-embedding technique adopts the Co-simulation model which composes PCB, QFN (Quad-FlatNo-leads) Package, and Chip for the PDN, applied Co-simulation model well corresponds with impedance from measured S-parameters up to 4 GHz at common measured and simulated points.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.19 no.12
• /
• pp.1-6
• /
• 2018

This study examined the quality improvement of printed circuit boards (PCBs) in relation to the power consumption for radar. The radar examined is currently in production and being used by the military. The PCB converts 28 V DC to 5 V DC but frequently malfunctions. Therefore, cause analysis was carried out. As a result, the power consumed by a certain communication IC was very high, and the heat generated by the high power consumption caused damage to the surrounding parts. Accordingly, it was changed to an improved communication IC that meets all the radar system specifications. System tests were carried out for the changed communication IC to check the impact on the system, and environmental tests were performed, which proved that the performance required by the radar system is satisfactory. As a result of this improvement, there has been no history of failure in this PCB so far. Therefore, the quality of this PCB has been improved.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.12 no.1
• /
• pp.18-23
• /
• 2012

We propose and implement a single-wire communication protocol for thermal management systems using thin film thermoelectric modules for 3D IC cooling. The proposed single-wire communication protocol connects the temperature sensors, located near hot spots, to measure the local temperature of the chip. A unique ID number identifying the location of each hot spot is assigned to each temperature sensor. The prototype chip was fabricated by a $0.13{\mu}m$ CMOS MPW process, and the operation of the chip is verified.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.12 no.2
• /
• pp.43-52
• /
• 2012

This paper presents and analyzes laboratory test results of Interference Cancellation Digital On Channel Regenerative Repeater(IC-DOCR) to broadcast digital television signals in the Advanced Television Systems Committee(ATSC) transmission systems using single frequency networks(SFN). IC-DOCR laboratory test is classified to receiver test, transmitter test, and feedback interference cancellation test. The receiver part includes random noise, single echo, multi-path ensembles, and adjacent channel interference test. The transmitter part includes out-of channel emission, equality of transmitting signal, and phase noise test. By the laboratory test, the receiver part of the IC-DOCR eliminates 28dB of feedback signal higher than the received signal and has 17.8dB at TOV(Threshold Of Visibility) under random noise environment. Also, the transmitter part satisfies the specification of US FCC(Federal Communications Commission) as well as maintains good output signal quality for guaranteeing more than SNR 30dB.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.1141-1144
• /
• 2003

For proper communication with various types of IC-Card, multiple IC-Card interface complying with the IC-Card standard (ISO7816) is embedded and realized as a peripheral on the 32-bit RISC based system-on-a-chip. It provides the generation of either 3.3V or 5V power supply for the operation of the inserted IC-Card as well. IC-Card interface is divided into an analog front-end (AFE) and a digital back-end (DBE). The embedded DC-DC converters suitable for driving IC-Cards are incorporated in the AFE. The chip design for multiple IC-Card interface is implemented on a standard 0.35${\mu}{\textrm}{m}$ triple-metal double-poly CMOS process and is packaged in a 352-pin plastic ball grid array (PBGA). The total gate count is about 400,000, excluding the internal memory. Die area is 7890${\mu}{\textrm}{m}$ $\times$ 7890${\mu}{\textrm}{m}$.