• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.430-439
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• 2004

This paper describes a design of 8192/2048-point FFT/IFFT processor (CFFT8k2k), which performs multi-carrier modulation/demodulation in OFDM-based DVB-T receiver. Since a large size FFT requires a large buffer memory, two design techniques are considered to achieve memory-efficient implementation of 8192-point FFT/IFFT. A hybrid structure, which is composed of radix-4 single-path delay feedback (R4SDF) and radix-4 single-path delay commutator (R4SDC), reduces its memory by 20% compared to R4SDC structure. In addition, a memory reduction of about 24% is achieved by a novel two-step convergent block floating-point scaling. As a result, it requires only 57% of memory used in conventional design, reducing chip area and power consumption. The CFFT8k2k core is designed in Verilog-HDL, and has about 102,000 Bates, RAM of 292k bits, and ROM of 39k bits. Using gate-level netlist with SDF which is synthesized using a $0.25-{\um}m$ CMOS library, timing simulation show that it can safely operate with 50-MHz clock at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. The functionality of the core is fully verified by FPGA implementation, and the average SQNR of 60-㏈ is achieved.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1868-1876
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• 2010

In this paper, we design a 256-bit EEPROM IP using only logic process-based devices. We propose EEPROM core circuits, a control gate (CG) and a tunnel gate (TG) driving circuit, to limit the voltages between the devices within 5.5V; and we propose DC-DC converters : VPP (=+4.75V), VNN (-4.75V), and VNNL (=VNN/3) generation circuit. In addition, we propose switching powers, CG_HV, CG_LV, TG_HV, TG_LV, VNNL_CG, VNNL_TG switching circuit, to be supplied for the CG and TG driving circuit. Simulation results under the typical simulation condition show that the power consumptions in the read, erase, and program mode are $12.86{\mu}W$, $22.52{\mu}W$, and $22.58{\mu}W$ respectively. Furthermore, the manufactured test chip operated normally and generated its target voltages of VPP, VNN, and VNNL as 4.69V, -4.74V, and -1.89V.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.3
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• pp.1393-1401
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• 2013

What is RFID Microchip tag attached to an object, the reader recognizes technology collectively, through communication with the server to authenticate the object. A variety of RFID tags, 13.56Mhz bandwidth RFID card, ISO/IEC 14443 standards based on NXP's Mifare tag occupies 72.5% of the world market. Of the Mifare tags, low cost tag Mifare Classic tag provided in accordance with the limited hardware-based security operations, protocol leaked by a variety of attacks and key recovery vulnerability exists. Therefore, in this paper, Cryptography Scheme and Secure Protocol for Safety Secure Scheme Construction in 13.56Mhz RFID have been designed. The proposed security scheme that KS generated by various fixed values and non-fixed value, S-Box operated, values crossed between LFSR and S-Box is fully satisfied spoofing, replay attacks, such as vulnerability of existing security and general RFID secure requirement. Also, It is designed by considering the limited hardware computational capabilities and existing security schemes, so it could be suit to Mifare Classic now.

• Journal of Navigation and Port Research
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• v.27 no.4
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• pp.443-447
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• 2003

In this work. using 0.2 GaAs modulation doped FET(MODFET), a high performance DBS downconverter MMIC was developed for direct broadcasting satellite (DBS) application. Without LNA, the downconverter MMIC showed a very low noise of 4.8 dB, which is lower by 3 dB than conventional ones. A low LO power of -10 dBm was required for the normal DBS operation of the downconverter MMIC. which reduced the power consumption via a removal of LO amplifier on MMIC. It required only a low power consumption of 175 mW, which is lower than 70 percent of conventional ones. The LO leakage power at IF output was suppressed to a lower level than 30 dBm, which removes a bulky LO rejection filter on a board. The fabricated chip, which include a mixer, If amplifiers. LO rejection filter, and active balun, exhibited a small size of $0.84{\times}0.9\textrm{mm}^2$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.12
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• pp.2366-2373
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• 2007

In this paper, a low-power and small-area asynchronous 1 kilobit EEPROM for passive UHF RFID tag chips is designed with $0.18{\mu}m$ EEPROM cells. As small area solutions, command and address buffers are removed since we design asynchronous I/O interface and data output buffer is also removed by using separate I/O. To supply stably high voltages VPP and VPPL used in the cell array from low voltage VDD, Dickson charge pump is designed with schottky diodes instead of a PN junction diodes. On that account, we can decrease the number of stages of the charge pump, which can decrease layout area of charge pump. As a low-power solution, we can reduce write current by using the proposed VPPL power switching circuit which selects each needed voltage at either program or write mode. A test chip of asynchronous 1 kilobit EEPROM is fabricated, and its layout area is $554.8{\times}306.9{\mu}m2$., 11% smaller than its synchronous counterpart.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.277-280
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• 2016

Currently, systems for finding missing children are composed of using communication between a QR code and RFID chip, as the use of a smartphone. However, the current systems for finding missing children have limitations in that children can only be found if there are people in the surrounding area; there is an economic burden on parents required to purchase a smartphone for their children; along with difficulties in finding the missing children without the assistance of those in the surrounding area in critical situations such as a kidnapping, due to the limited duration of the battery life. In order to solve such problems, approaches need to be made from two perspectives: having someone in the surrounding area; and absence of anyone in the surrounding area. This thesis is centered on the development of a IoT (Internet of Things) system for finding missing children that combines two methods, namely, the method of finding missing children without a guardian in the surrounding area -within the limited space in which AP is installed by using a beacon and open source hardware being highlighted as the IoT technology - and the method of finding missing children with the smartphone application in which each individual becomes the Access Point (AP). The Main purpose is to provide accurate information of missing children's location for the 2situations and it is found that the accuracy of smartphones APP is 97.7% and security device AP is 91.1%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.7
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• pp.1071-1077
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• 2022

A security SoC that can be used to implement elliptic curve cryptography (ECC) based public-key infrastructures was designed. The security SoC has an architecture in which a hardware accelerator for the elliptic curve digital signature algorithm (ECDSA) is interfaced with the Cortex-A53 CPU using the AXI4-Lite bus. The ECDSA hardware accelerator, which consists of a high-performance ECC processor, a SHA3 hash core, a true random number generator (TRNG), a modular multiplier, BRAM, and control FSM, was designed to perform the high-performance computation of ECDSA signature generation and signature verification with minimal CPU control. The security SoC was implemented in the Zynq UltraScale+ MPSoC device to perform hardware-software co-verification, and it was evaluated that the ECDSA signature generation or signature verification can be achieved about 1,000 times per second at a clock frequency of 150 MHz. The ECDSA hardware accelerator was implemented using hardware resources of 74,630 LUTs, 23,356 flip-flops, 32kb BRAM, and 36 DSP blocks.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.1
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• pp.219-227
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• 2017

Current military command information system uses electronic equipment a lot on which semiconductor chip is attached. It seems its' importance will increase more with latest information communication technology developing. Electronic equipment which uses electricity contains regular tolerance to high output electric signal. And EMC specification is the standardized of this electronic equipment's tolerance. On the other hand, the Institute of Atomic Energy Research has ever declared that high output electromagnetic pulse(EMP) will be broken out within the radius of 170Km when 10kt nuclear explosion occurs at an altitude of 40Km above Seoul. Then, the region suffer from the damage of most electronic equipments. Therefore, the norm to protect the influences in that case is defined by EMP protection specification. Most common electronic equipments meet the EMC norm, but there is no way to check whether they meet the EMP norm or not. That is because it is difficult to check whether they meet EMP protection norm and is on the matter of cost. Except inevitable cases, there is no review of checking whether they meet the norm or not. Considering the above, in this research, we speculate about the measures to improve military EMP protection ability by analyzing the EMC-EMP correlation and checking the EMP protection ability of general electronic equipment through the analysis.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.143-148
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• 2001

PbWO$_4$ can be densified at 85$0^{\circ}C$ and it shows fairy good microwave dielectric properties; dielectric constant($\varepsilon$$_{r}$) of 21.5, quality factor(Q $\times$f$_{0}$) of 37,224 GHz, and temperature coefficient of resonant frequency($\tau$/suf f/) of -31ppm/$^{\circ}C$. Due to its low sintering temperature, PbWO$_4$ can be used as a multilayered chip component at microwave frequency with high electrical performance by using high conductive electrode metals such as Ag and Cu. However, in order to use this material for microwave communication devices, the $\tau$$_{f}$ of PbWO$_4$ must be stabilized to near zero with high Q$\times$f$_{0}$. In present study, PbWO$_4$ was modified by adding TiO$_2$, B$_2$O$_3$, and CuO in order to improve the microwave dielectric properties without increasing the sintering temperature. The addition of TiO$_2$ increased the $\tau$$_{f}$ and $\varepsilon$$_{r}$, due to its high rr(200ppm/$^{\circ}C$) and $\varepsilon$$_{r}$(100). However, the addition of TiO$_2$ reduced the Q$\times$f$_{0}$ value. When the mot ratio of PbWO$_4$ and TiO$_2$ was 0.913:7.087, near zero $\tau$$_{f}$(0.2ppm/$^{\circ}C$) was obtaibed with $\varepsilon$$_{r}$=22.3, and Q$\times$f/$_{0}$=21,443GHz. With this composition, various amount of B$_2$O$_3$ and CuO were added in order to improve the quality factor. The addition, of B$_2$O$_3$ decreased the $\varepsilon$$_{r}$. However, increased Q$\times$f$_{0}$ and $\tau$$_{f}$. When 2.5 wt% of B$_2$O$_3$ was added to the 0.913PbWO$_4$-0.087TiO$_2$ ceramic, $\tau$$_{f}$ =8.2, $\varepsilon$$_{r}$=20.3, Q$\times$f$_{0}$=54784 GHz. When CuO added to the 0.913PbWO$_4$-0.087TiO$_2$ ceramic, $\tau$$_{f}$ was continuously decreased. And $\varepsilon$$_{r}$ . and Q$\times$f$_{0}$ were increased up to 1.0 wt% then decreased. At 0.1 wt% of CuO addition, the 0.913PbWO$_4$-7.087Ti0$_2$ Ceramic Showed $\varepsilon$$_{r}$=23.5, $\tau$$_{f}$=4.4ppm/$^{\circ}C$, and Q$\times$f$_{0}$=32,932 GHz.> 0/=32,932 GHz.X>=32,932 GHz.> 0/=32,932 GHz.

• Journal of Intelligence and Information Systems
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• v.20 no.2
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• pp.163-178
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• 2014

Following research proposes "Virtualization of Smart Cards (ViSCa)" which is a security system that aims to provide a multi-device platform for the deployment of services that require a strong security protocol, both for the access & authentication and execution of its applications and focuses on analyzing Virtualization of Smart Cards (ViSCa) platform-based mobile payment service by comparing with other similar cases. At the present day, the appearance of new ICT, the diffusion of new user devices (such as smartphones, tablet PC, and so on) and the growth of internet penetration rate are creating many world-shaking services yet in the most of these applications' private information has to be shared, which means that security breaches and illegal access to that information are real threats that have to be solved. Also mobile payment service is, one of the innovative services, has same issues which are real threats for users because mobile payment service sometimes requires user identification, an authentication procedure and confidential data sharing. Thus, an extra layer of security is needed in their communication and execution protocols. The Virtualization of Smart Cards (ViSCa), concept is a holistic approach and centralized management for a security system that pursues to provide a ubiquitous multi-device platform for the arrangement of mobile payment services that demand a powerful security protocol, both for the access & authentication and execution of its applications. In this sense, Virtualization of Smart Cards (ViSCa) offers full interoperability and full access from any user device without any loss of security. The concept prevents possible attacks by third parties, guaranteeing the confidentiality of personal data, bank accounts or private financial information. The Virtualization of Smart Cards (ViSCa) concept is split in two different phases: the execution of the user authentication protocol on the user device and the cloud architecture that executes the secure application. Thus, the secure service access is guaranteed at anytime, anywhere and through any device supporting previously required security mechanisms. The security level is improved by using virtualization technology in the cloud. This virtualization technology is used terminal virtualization to virtualize smart card hardware and thrive to manage virtualized smart cards as a whole, through mobile cloud technology in Virtualization of Smart Cards (ViSCa) platform-based mobile payment service. This entire process is referred to as Smart Card as a Service (SCaaS). Virtualization of Smart Cards (ViSCa) platform-based mobile payment service virtualizes smart card, which is used as payment mean, and loads it in to the mobile cloud. Authentication takes place through application and helps log on to mobile cloud and chooses one of virtualized smart card as a payment method. To decide the scope of the research, which is comparing Virtualization of Smart Cards (ViSCa) platform-based mobile payment service with other similar cases, we categorized the prior researches' mobile payment service groups into distinct feature and service type. Both groups store credit card's data in the mobile device and settle the payment process at the offline market. By the location where the electronic financial transaction information (data) is stored, the groups can be categorized into two main service types. First is "App Method" which loads the data in the server connected to the application. Second "Mobile Card Method" stores its data in the Integrated Circuit (IC) chip, which holds financial transaction data, which is inbuilt in the mobile device secure element (SE). Through prior researches on accept factors of mobile payment service and its market environment, we came up with six key factors of comparative analysis which are economic, generality, security, convenience(ease of use), applicability and efficiency. Within the chosen group, we compared and analyzed the selected cases and Virtualization of Smart Cards (ViSCa) platform-based mobile payment service.