• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.913-920
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• 2011

In this paper, a logic process based 1-kbit EEPROM IP for RFID tag chips of 900MHz is designed. The cell array of the designed 1-kbit EEPROM IP is arranged in a form of four blocks of 16 rows x 16 columns, that is in a two-dimensional arrangement of one-word EEPROM phantom cells. We can reduce the IP size by making four memory blocks share CG (control gate) and TG (tunnel gate) driver circuits. We propose a TG switch circuit to supply respective TG bias voltages according to operational modes and to keep voltages between devices within 5.5V in terms of reliability in order to share the TG driver circuit. Also, we can reduce the power consumption in the read mode by using a partial activation method to activate just one of four memory blocks. Furthermore, we can reduce the access time by making BL (bit line) switching times faster in the read mode from reduced number of cells connected to each column. We design and compare two 1-kbit EEPROM IPs, two blocks of 32 rows ${\times}$ 16 columns and four blocks of 16 rows ${\times}$ 16 columns, which use Tower's $0.18{\mu}m$ CMOS process. The four-block IP is smaller by 11.9% in the layout size and by 51% in the power consumption in the read mode than the two-block counterpart.

• The Journal of the Korea Contents Association
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• v.8 no.6
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• pp.1-7
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• 2008

The paper is to solve the problem of existing sound system, which has difficulties of system organization and the increase of additional install cost and unfriendly interior. To solve the existing system, we drew the new sound system based on PLC and studied it. A transmitter and a receiver were designed using the PLC chip INT5500CS. Sound system was configured with a CD player that sound signals are sent from the transmitter and a speaker connected to the receiver. For analysis of characteristics of this system, a USBPre external sound card and Smaart Live 5 which is a PC-based sound measuring program were added. As a result of our experiment, the measured signal level is $2{\sim}3$[dB] lower than reference signal, latency is 16.69[ms] and the specific character of coherency is bad in high frequency band. Otherwise, this system transmits and receives signals over 90[%] in good condition as a result of measuring pink noise, frequency(1kHz), and phase, magnitude. In view of the result so far achieved, the system designed our team has excellent performance, it resolves defect of existing audio signal transmition system.

• The Journal of the Korea Contents Association
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• v.4 no.4
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• pp.123-131
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• 2004

Internet is absolutely contributed to information technology revolution nowadays. Internet services such as voice and data, etc. are provided home or small office via home gateway. The development of communication equipment via home gateway is implemented rapidly, and its product various. This paper presents the design and implementation of the VoIP equipment including the telephone function based on the embedded environment and being connected to the home gateway and the PC because of taking 2-ethernet LAN ports. As developing environment, the STLC1502 developed at ST Microelectronics as single chip solution, VxWorks as RTOS, and C language as coding mechanism are used. The verification of the developed systems for the voice test is carried out for the gatekeeper via Internet. The performance parameter is considered as the call processing capacity measuring the time of the call setup and clearing, and the data processing capacity for the file transfer. As a call setup and clearing is about 95ms, the call processing capacity is about 10 calls per second. The data processing capacity is 5.7Mbps in case of file transfer of server and client environment. Therefore the performance result is satisfied in the aspect of the call processing time and the data transfer time in Internet.

• Journal of Digital Convergence
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• v.11 no.4
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• pp.221-227
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• 2013

RFID is an automatic identification technology that can control a range of information via IC chips and radio communication. Also known as electronic tags, smart tags or electronic labels, RFID technology enables embedding the overall process from production to sales in an ultra-small IC chip and tracking down such information using radio frequencies. Currently, RFID-based application and development is in progress in such fields as health care, national defense, logistics and security. RFID structure consists of a reader that reads tag information, a tag that provides information and the database that manages data. Yet, the wireless section between the reader and the tag is vulnerable to security issues. To sort out the vulnerability, studies on security protocols have been conducted actively. However, due to difficulties in implementation, most suggestions are concerned with theorem proving, which is prone to vulnerability found by other investigators later on, ending up in many troubles with applicability in practice. To experimentally test the security of the protocol proposed here, the formal verification tool, CasperFDR was used. To sum up, the proposed protocol was found to be secure against diverse attacks. That is, the proposed protocol meets the safety standard against new types of attacks and ensures security when applied to real tags in the future.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.10
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• pp.2237-2246
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• 2012

A bias circuit required for an oral sensor is manufactured inside the oral sensor chip to reduce its size and cost. The proposed DC-DC converter supplies the required reference and bias currents for their corresponding regulators by using IREF of the reference current generator. Their target voltages of the voltage regulators are regulated by the negative mechanism by generating their reference voltages required for their corresponding regulators. In addition, a constant current IB0/IB1 is supplied by being mirrored by a current mirror ratio and then VREF is generated. It is confirmed by measurements that the average volatge, ${\sigma}$, and $4{\sigma}$ of the designed DC-DC converter for intra oral sensors with a $0.18{\mu}m$ X-ray CMOS process are within their required ranges. And the line-pair pattern image shows a high-resolution characteristic without blurring. Also, a good oral image can be obtained.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.7
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• pp.750-755
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• 2003

This paper proposes a new three-line balun. The equivalent circuit of the proposed three-line balun is presented, and impedance matrix［Z］of the equivalent circuit is derived from the relationship between the current and voltage at each port. The design equation for a given set of balun impedance at input and output ports is presented using［S］parameters, which is transferred fom impedance matrix,［Z］. To demonstrate the feasibility and validity of design equation, multi-layer ceramic(MLC) chip balun operated in the 2.4 GHz ISM band frequency is designed and fabricated by the use of the low temperature co-fired ceramic(LTCC) technology. By employing both the proposed new three-line balun equivalent circuit and multi-layer configuration provided by LTCC technology, the 2012 size MLC balun is realized. Measured results of the multi-layer LTCC three-line balun match well with the full-wave electromagnetic simulation results, and measured in band-phase and amplitude balances over a wide bandwidth are excellent. This proposed balun is very easily applicable to multi-layer structure using LTCC as shown in the paper, and also can be realized with microstrip lines on PCB. This distinctive performance is very favorable for wireless communication systems such as wireless LAN(Local Area Network) and Bluetooth applications.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.5
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• pp.445-453
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• 2016

This paper presents the implementation and design of the 1T-1R wireless HD video streaming systems over 28 GHz mmWave frequency using 3GPP LTE-TDD standard on NI USRP RIO SDR platform. The baseband of the system uses USRP RIO that are stored in Xilinx Kintex-7 chip to implement LTE-TDD transceiver modem, the signal that are transceived from USRP RIO up or down converts to 28 GHz by using self-designed 28 GHz RF transceiver modules and it is finally communicated HD video data through self-designed $4{\times}8$ sub array antennas. It is that communication method between USRP RIO and Host PC use PCI express ${\times}4$ to minimize delay of data to transmit and receive. The implemented system show high error vector magnitude performance above 25.85 dBc and to transceive HD video in experiment environment anywhere.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.3
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• pp.50-56
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• 2010

In this paper, compact broad-band antenna using circular spiral slot and CPW (coplanar waveguide) feed is proposed. The proposed antenna is designed on the same plane of the substrate by using CPW fed structure, archimediean spiral slot structure. So it was achieved both the size of compact antenna and the broad band. A archimediean spiral slot structure is introduced for resonance of medium band operation. The distances of a CPW feeder line and a ground plane are modified for impedance matching and lower/higher band operation. The proposed antenna has a compact size ($8mm\;{\times}\;13mm$) and it is etched on the FR-4 (relative dielectric constant 4.4, thickness 0.8mm) dielectric substrate. The simulated impedance bandwidth (VSWR $\leq$ 2) and maximum gain of the proposed antenna are 5.98GHz (4.1GHz ~ 10.08GHz) and 3.97dBi, respectively. The measured impedance bandwidth (VSWR $\leq$ 2) and maximum gain of the proposed antenna are 6.02GHz (4.48GHz ~ 10.5GHz) and 2.68dBi, respectively. The simulation and measured result shows good impedance matching and radiation pattern over the interesting frequency bands. It can be applied to antenna of broad-band wireless communication system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.486-495
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• 2006

In this paper, a low-power 1Kb synchronous EEPROM is designed with flash cells for passive UHF RFID tag chips. To make a low-power EEPROM, four techniques are newly proposed. Firstly, dual power supply voltages VDD(1.5V) and VDDP(2.5V), are used. Secondly, CKE signal is used to remove switching current due to clocking of synchronous circuits. Thirdly, a low-speed but low-power sensing scheme using clocked inverters is used instead of the conventional current sensing method. Lastly, the low-voltage, VDD for the reference voltage generator is supplied by using the Voltage-up converter in write cycle. An EEPROM is fabricated with the $0.25{\mu}m$ EEPROM process. Simulation results show that power dissipations are $4.25{\mu}W$ in the read cycle and $25{\mu}W$ in the write cycle, respectively. The layout area is $646.3\times657.68{\mu}m^2$.

• The KIPS Transactions:PartC
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• v.11C no.1
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• pp.141-148
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• 2004

Recently, the demand of broadband communications such as high-speed internet, HDTV, 3D-HDTV and ATM backbone network has been increased drastically. For transmitting the broad-bandwidth data using wireless network, it is needed to use ka-band frequency. However, the use of this ka-band frequency is seriously affected to the received data performance by rain fading and atmospheric propagation loss at the Ka-band satellite communication link. So, we need adaptive MODEM to endure the degraded performance by channel environment. In this paper, we will present the structure and design of the 155Mbps adaptive Modem adaptively compensated against channel environment. In order to compensate the rain attenuation over the ka-band wireless channel link, the adaptive coding schemes with variable coding rates and the multiple modulation schemes such as trellis coded 8-PSK, QPSK, and BPSK are adopted. And the blind demodulation scheme is proposed to demodulate without Information of modulation mode at the multi-mode demodulator, and the fast phase ambiguity resolving scheme is proposed. The design and simulation results of adaptive Modem by SPW model are provided. This 155Mbps adaptive MODEM was designed and implemented by single ASIC chip with the $0.25\mu{m}$ CMOS standard cell technology and 950 thousand gates.