• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1082-1088
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• 2005

Generating fast round key in AES Rijndael algorithm using three key sizes, such as 128, 192, and 256-bit keys is a critical factor to develop high throughput AES processors. In this paper, we propose on-the-fly round key generator which is applicable to the pipelined and non-pipelined AES processor in which cipher and decipher nodes must be implemented on a chip. The proposed round key generator has modular and area-and-time efficient structure implemented with simple connection of two key expander modules, such as key_exp_m and key_exp_s module. The round key generator for non-pipelined AES processor with support of three key lengths and cipher/decipher modes has about 7.8-ns delay time under 0.25um 2.5V CMOS standard cell library and consists of about 17,700 gates.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.941-944
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• 2003

This paper implement Telemetry System which is used Bluetooth. This System propose system which can detect a total amount of gas, electricity or water without a motorman, at home. BlueTooth is a close range wireless communication technology which uses a wireless frequency 2.4GHz and has a high trust and self - error correction technology according to a low power consumption quality and a high-speed frequency hopping. This makes get a high trust concerning a data transmission than an existing modem. In addition, though wireless modem is restricted by a minimal of a wireless terminal, it will be possible to coincide with the function of the portable with the low power consumption quality by using Bluetooth. And as the system on a chip of module progresses, the possibility of the snail size is present. And, Motorman who use mobility of embedded system can detect detect a total amount of gas, electricity or water outdoor. Embedded system use ARM processor that is low power processor. So it ran use long time efficiently.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.3
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• pp.571-578
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• 2012

In this paper, we propose two main points. The first is the constraint for logic synthesis, and the second is an efficient logic synthesis method. Logic synthesis is a process to obtain the gate-level netlist from RTL (register transfer level) codes using logic mapping and optimization with the specified constraints. The result of logic synthesis is tightly dependent on constraint and logic synthesis method. Since the size and timing can be dramatically changed by these, we should precisely consider them. In this paper, we present the considering items in the process of logic synthesis by using our experience and experimental results. The proposed techniques was applied to a circuit with the hardware resource of about 650K gates. The synthesis time for the hybrid method was reduced by 47% comparing the bottom-up method and It has better timing property about slack than top-down method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.8B
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• pp.745-751
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• 2002

The performance of existing CDMA-type multiple access data transmission systems is limited by interferences due to adverse mobile communication channel characteristics. Among them, the multi-user interference becomes one of the major performance degradation factors because the signal-to-signal orthogonality can be easily perturbed when numerous user signals are distorted by multipath fading channels and mixed together. In order to enhance the performance of CDMA-type systems by suppressing the multi-user interference, we have adopted chip-based cyclic prefix insertion along with adaptive one-tap DFE equalization into MC-DS-CDMA, which is known for its robustness in the frequency selective multipath fading channel environment. In order to assess the performance of the proposed system, a set of computer simulations is performed in the reverse link in which each user signal undergoes different multipath Rayleigh fading. The results show us a superior performance of our system over other CDMA systems in terms of SNR to BER measurements.

• Information and Communications Magazine
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• v.9 no.9
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• pp.72-85
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• 1992

The throughput requirement for many digital signal processing is such that multiple processing units are essential for real-time implementation. Advances in VLSI technology make it feasible to design and implement computer systems consisting of a large number of function units. The research on a very high throughput VLSI architecture for digital signal processing applications requires the development of an algorithm, decomposition scheme which can minimize data communication requirements as well as minimize computational complexity. The objectives of the research are to investigate computationally efficient algorithms for solution of the class of problems which can be modeled as DLSI systems or adaptive system, and develop VLSI architectures and associated multiprocessor systems which can be used to implement these algorithms in real-time. A new VLSI architecture for real-time 2-D digital signal processing applications is proposed in this research. This VLSI architecture extends the concept of having a single processing units in a chip. Because this VLSI architecture has the advantage that the complexity and the number of computations per input does not increase as the size of the input data in increased, it can process very large 2-D date in near real-time.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.3
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• pp.209-215
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• 2006

This paper was proposed Intelligent and wireless USN/RFID module system that can overcome disadvantage of existing RFID system with no sensing module and wire communication. The proposed USN/RFID system was designed and fabricated. After fabricating new system, we analyzed the characteristics of USN/RFID module. After design VCO block that is point circuit to develop next generation system one chip of RFID system, we were carried out simulation and verified the validity. this paper was showed that VCO system was enough usable in wireless network module. USN/RFID Reader module shows superior result that validity awareness distance corresponds to 30 M in the case of USN and to 5 M in RFID Reader's case and 900 MHz of commercial frequency does practical use enoughly in range of high frequency. The USN/RFID Reader module is considered to act big role to Ubiqitous industry offering computing surrounding of new concept that is intelligence type service and that was associated to real time location system(RTLS), environment improvement/supervision, national defense, traffic administration etc.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1884-1891
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• 2012

In this paper, we design the sliding correlator SS transceiver which supports short message service. We also analyze the PN code acquisition circuit that is essential for spread spectrum receiver. Using Maxplus II tool provided by altera Co., Ltd, we have designed PN code generator, and sliding correlator for PN code acquisition. Then, they have been made into FPGA by way of EPM7064SLC44-10 - a chip of Altera Co., Ltd. Additionally, we have designed delay clock circuit which is faster than the clock of Tx PN clock, designed switching circuit to control the clock rate and data demodulation circuit. The performance of the transceiver is evaluated from the experimental results. Especially, the performance of PN code acquisition accomplished by sliding correlator which is very important to evaluate spread spectrum receiver is evaluated with the comparison of the lock states.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.2003-2008
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• 2012

A drive system is necessary to operate LED by an LED illumination system. Because Switched Mode Power Supply (SMPS) is higher in efficiency in the large capacity than Linear Regulator, it is used mainly and controls this in an analog form or digital method. A MCU and a DSP of the digital control central processing unit were higher in a unit price than existing analog control chip, so that an approach was not easy for application of SMPS. But it can take the earnings by it lets you integrate various digital control features like an LED illumination system in one MCU, and realizing a whole system. In this paper, we suggest the algorithm that can improve LED driving current in applying such a digital control method using low-priced type MCU.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.10
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• pp.2209-2216
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• 2011

In this paper, we design a 32-bit eFuse OTP memory for PMICs using MagnaChip's $0.18{\mu}m$ process. We solve a problem of an electrical shortage between an eFuse link and the VSS of a p-substrate in programming by placing an n-well under the eFuse link. Also, we propose a WL driver circuit which activates the RWL (read word-line) or WWL (write word-line) of a dual-port eFuse OTP memory cell selectively when a decoded WERP (WL enable for read or program) signal is inputted to the eFuse OTP memory directly. Furthermore, we reduce the layout area of the control circuit by removing a delay chain in the BL precharging circuit. We'can obtain an yield of 100% at a program voltage of 5.5V on 94 manufactured sample dies when measured with memory tester equipment.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.1
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• pp.63-70
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• 2015

In this paper, a receiver has been developed in a $0.11-{\mu}m$ CMOS technology for 900 MHz RFID communication system applications. The receiver is composed of an envelope detector, a low-pass-filter, a comparator, D flip-flops, as well as an oscillator to provide the clock for digital blocks. The receiver is designed for low power consumption, which would be suitable for passive RFID tags. In this circuit, a digital data slicer was employed instead of the conventional analog data slicer in order to reduce the power consumption. The clock frequency is 1.68 MHz and the circuit operates with a power consumption as small as $5{\mu}W$. The chip size is $325{\mu}m{\times}290{\mu}m$ excluding the probing pads.