• Title/Summary/Keyword: Communication Chip

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Throughput Analysis of Wireless Transmission Platform using Multiple Wireless Chips for M2M Networks (M2M 어플리케이션 지원을 위한 무선 결합 전송 플랫폼의 전송률 분석)

  • Wang, Hanho;Woo, Choongchae
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.63 no.3
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    • pp.195-199
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    • 2014
  • Various M2M applications have different quality-of-service(QoS) requirements to be implemented practically. QoS requirements are normally data rate and delay constraint. However, there are limited number of wireless communication chip solutions which cannot support QoS requirements for all M2M application. Hence, aggregated usage of plural wireless communication chip solutions should be needed to implement M2M applications. In this paper, we consider the case that two wireless communication chips using random access protocol work together to transmit data of an M2M application. In such case, data rate and delay performance are mathematically analyzed. In our results, practical data rate can be improved from 2.5 to 7 times while delay constraints are satisfied if we simply use two wireless communication chips together.

MMIC Self Oscillating Mixer

  • Kim, Young-Gi;Hwang, Chul;Jung, Jin-Yang;Yoon, Shin-Young
    • Proceedings of the IEEK Conference
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    • 1999.11a
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    • pp.291-294
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    • 1999
  • This paper presents a GaAs MESMET self oscillating mixer for high efficiency L-band frequency conversion with small chip area consumption. Main circuit topology is consist of cascoded two FET with resonating part. The circuit is designed as unstably nonlinear for limited frequency band. FET with drain shorted to source is used for frequency tuning element. Linear conversion gain of -18.83 ㏈ is achieved with 9mA and 4V consumption. Input 1㏈ compression point is more than 11㏈m. The chip area is 1.4$\times$1.4 mm.

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Smart Chip Design using High Speed Program Algorithm (고속프로그램 알고리즘을 이용한 스마트 칩 설계)

  • Kim, Tae-Min;Shin, Gun-Soon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.11 no.8
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    • pp.1564-1573
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    • 2007
  • Bulk of toner residual quantity detection return trip conglutinated in toner of using printer current is comparative big state by using PCB substrate, therefore is incongruent to use in light weight print miniaturized more. Return trip this development miniaturizes such as this by doing one chip competitive product develop chip has to be conglutinated compulsorily in toner used to printer announced since 2005 years. Therefore, demand of chip to be used in forward revival market may be thriving. Production of revival toner is impossible by chip conglutinated to printer to meaning that manage information of toner cut ridge that universal laser printer makers are used in printer and do customer service. In this paper, we develops chip conglutinated compulsorily to produce revival toner.

The Optimum Structure Design of 1005 RF Chip Inductors for GHz Band (GHz 대역을 위한 1005 RF 칩 인덕터의 최적 구조 설계)

  • Kim, Jae-Wook;Ryu, Chang-Keun
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.785-788
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    • 2005
  • In this study, micro-scale, high-performance, solenoid-type RF chip inductors were investigated. The size of the RF chip inductors fabricated in this work was $1.0{\times}0.5{\times}0.5mm^3$ The material and shape of the core were 96% $Al_2O_3$ and I-type. The material and number of turn of coil were copper (Cu) and 6. The diameter ($40{\mu}m$) of coil and length (0.35mm) of solenoid were determined by a Maxwell three-dimensional field simulator to maximize the performance of the inductors. High frequency characteristics of the inductance (L) and quality-factor (Q) of developed inductors were measured using an RF Impedance/Material Analyzer (HP4291B with HP16193A test fixture). The inductors developed have inductances of 10.8nH and quality factors of 25.2 at 250MHz, and show results comparable to those measured for the inductors prepared by CoilCraftTm that is one of the best chip inductor company in the world. The simulated data predicted the high-frequency data of the Land Q of the inductors developed well.

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A study on the Field Solver Based pad effect deembedding technique of on-chip Inductor (온칩 인덕터의 필드 솔버 기반의 패드 효과 디임베딩 방법 연구)

  • Yoo, Young-Kil;Lee, Han-Young
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.44 no.7 s.361
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    • pp.96-104
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    • 2007
  • In this paper, the field solver based deembedding technique for the on-chip inductors to deembed the pad and surrounding ground effect was described, and the results from field solver based deembedding techniques and measurement based matrix calculation method were compared. In addition, LNA circuit is designed by using deembedded inductors and fabricated by using standard $0.25{\mu}m$ CMOS process, in the range over the 2.5GHz it shows the good agreements between measurement and simulation results when the proper deembedding was adapted. Supposed deembedding techniques can be used to get the pure on-chip devices's values and adapted to design accurate RFIC circuit design.

Mapping and Scheduling for Circuit-Switched Network-on-Chip Architecture

  • Wu, Chia-Ming;Chi, Hsin-Chou;Chang, Ruay-Shiung
    • ETRI Journal
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    • v.31 no.2
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    • pp.111-120
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    • 2009
  • Network-on-chip (NoC) architecture provides a highper-formance communication infrastructure for system-on-chip designs. Circuit-switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real-time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in $6{\times}6$6, $8{\times}8$, and $10{\times}10$ mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit-switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.

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Design and Implementation of FMCW Radar Based on two-chip for Autonomous Driving Sensor (자율주행센서로서 개발한 2-chip 기반의 FMCW MIMO 레이다 설계 및 구현)

  • Choi, Junhyeok;Park, Shinmyong;Lee, Changhyun;Baek, Seungyeol;Lee, Milim
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.22 no.6
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    • pp.43-49
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    • 2022
  • FMCW(Frequency Modulated Continuous Wave) Radar is very useful for vehicle collision warning system and autonomous driving sensor. In this paper, the design and implementation of FMCW radar based on two chip MMIC developed as an autonomous driving sensor was described. Especially, generation of frame-based and chirp-based waveform generation and signal processing are mixed to have the strength of maximum detection speed and compensation of speed. This implemented system was analyzed for performance and commercialization potential through lab. test and driving test in K-city.

The Performance of Chip Level Detection for DS/CDMA Operating in LEO Satellite Channel (저궤도 위성통신을 위한 칩레벨 DS/CDMA 시스템의 성능 평가에 관한 연구)

  • Jae-Hyung Kim;Seung-Wook Hwang
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.2 no.4
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    • pp.553-558
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    • 1998
  • We present in this paper the ture union bound of the performance of chip level detection for coded DS/CDMA system operating in Rician fading channels such as LEO satellite mobile radio where the maximum doppler frequency is very high. The main objective of this paper is to calculate the exact doe union bound of BER performance of different performance of different quadrature detectors and to find a optimum spreading factor as a function of fade rate. The rationale of using multiple chip detection is to reduce the effective fade rate or variation. We considered chip level differential detection, chip level maximum likelihood sequence estimation, noncoherent detection and coherent detection with perfect channel state information as a reference.

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A software-controlled bandwidth allocation scheme for multiple router on-chip-networks

  • Bui, Phan-Duy;Lee, Chanho
    • Journal of IKEEE
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    • v.23 no.4
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    • pp.1203-1207
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    • 2019
  • As the number of IP cores has been increasing in a System-on-Chip (SoC), multiple routers are included in on-chip-networks. Each router has its own arbitration policy and it is difficult to obtain a desired arbitration result by combining multiple routers. Allocating desired bandwidths to the ports across the routers is more difficult. In this paper, a guaranteed bandwidth allocation scheme using an IP-level QoS control is proposed to overcome the limitations of existing local arbitration policies. Each IP can control the priority of a packet depending on the data communication requirement within the allocated bandwidth. The experimental results show that the proposed mechanism guarantees for IPs to utilize the allocated bandwidth in multiple router on-chip-networks. The maximum error rate of bandwidth allocation of the proposed scheme is only 1.9%.