• International Journal of Internet, Broadcasting and Communication
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• v.16 no.4
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• pp.265-272
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• 2024

Semiconductors are crucial components in communication technology, playing important roles in various communication systems. They are essential for signal processing, data transmission, and ensuring the stability of communication networks. In particular, high-performance semiconductor chipsets and processors enable ultra-fast data transmission and ultra-low latency in communication technology. For example, semiconductors are indispensable in smartphones, wireless networks, and satellite communication systems. For semiconductor packaging products, nondestructive internal analysis for defect analysis and process improvement without causing deformation of system packaging is an important part of the product development process. In this study, nondestructive analysis techniques using X-ray equipment are discussed. The results of this study can provide fast and accurate nondestructive analysis of semiconductor packaging products and can play a significant role in supporting the growth of the communication industry.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.279-284
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• 2005

We investigated the impedance matching characteristics of UHF-band RFID tag antenna and tag chip for increased reading range. A voltage multiplier designed using 0.4 $\mu$m zero-$V_T$ MOSFET showed that DC output voltage of about 2 V can be obtained using standard CMOS process. The input impedance of the voltage multiplier was examined to achieve impedance matching to the RFID tag antenna using analytical and numerical approaches. The input impedance of the voltage multiplier could be varied in a wide range by selecting the size of MOSFET and the number of multiplying stages, and thus can be impedance matched to a tag antenna in presence of other tag circuit blocks. A meander line inductively-coupled RFID tag antenna operating at UHF band also shows the feasibility of impedance matching to tile RFID tag chip.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.993-997
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• 2004

A data error inspection algorithm for wireless digital data communication was developed. Original data converted By wireless digital data error inspection algorithm. Wireless digital data is high possibility to get distortion and lose by noise and barrier on wireless. If the data check damaged and lost at receiver, can't make it clear and can't judge whether this data is right or not. Therefore, by wireless transmission data need the data error inspection algorithm in order to decrease the data distortion and lose and to monitoring the transmission data as real time. This study consists of RF station for wireless transmission, Water Level Meter station for water level measurement and Error inspection algorithm for error check of transmission data. This study is also that investigation and search for error inspection algorithm in order to wireless digital data transmission in condition of the least data's damage and lose. Designed transmitter and receiver with one - chip micro process to protect to swell the volume of circuit. Had designed RF transmitter - receiver station simply by means of ATMEL one - chip micro processing the systems. Used 10mW of the best RF power and 448MHz-449MHz on frequency band which is open to public touse free within the limited power.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.3
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• pp.410-415
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• 2002

This paper describes the implementation of a SoC(System-on-a-Chip) and an ISDN communication terminal by the SoC in ISDN network. The SoC has been developed with the functions of 32-bit ARM7TDMI RISC core processor, network connection with S/T interface, TDM--bus interface and voice codec, user interface. And we also review the developed software structure and the ISDN service protocol procedures which are working on the SoC. And finally this paper describers a structure of an ISDN terminal equipment using the implemented SoC and terminal software.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.1
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• pp.683-690
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• 2015

Two basic FFT(Fast Fourier Transform) algorithms are the DIT(Decimation-In-Time) and the DIF (Decimation-In-Frequency). In spite of the advantage of the DIT algorithm is to generate a sequential output, various structures have not been made. In this paper, a new DIT Radix-4 FFT butterfly structure are proposed and implemented using Verilog coding. Through synthesis, it is shown that the 64-point FFT is implemented by 6.78 million gates. Since the proposed FFT structure has the advantage of a sequential output, it can be used in OFDM communication SoC(System on a Chip) which need a high speed FFT output.

• The Journal of the Acoustical Society of Korea
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• v.16 no.3
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• pp.86-93
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• 1997

A Design & Simulation Tools of Surface Acoustic Wave(SAW) Filters for Mobile Communication Systems, which is based on Optimization of Impulse Samples with Object Function of Amplitude, Ripple and Group Delay Characteristics, is developed and is also evaluated by designning and simulating the SAW IF Filter for PCS. In Optimization Process, fast calculation algorithm of Object Function is proposed. With this Design Tools, Transversal SAW IF Filters can be easily designed under limited conditions of small chip size and package size. It may be also applicable to wide Band Pass Filters in future Communication Systems such as FPLMTS.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.202-211
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• 2014

The bulk current injection (BCI) and direct power injection (DPI) method have been established as the standards for the electromagnetic susceptibility (EMS) test. Because the BCI test uses a probe to inject magnetically coupled electromagnetic (EM) noise, there is a significant difference between the power supplied by the radio frequency (RF) generator and that transferred to the integrated circuit (IC). Thus, the immunity estimated by the forward power cannot show the susceptibility of the IC itself. This paper derives the real injected power at the failure point of the IC using the power transfer efficiency of the BCI method. We propose and mathematically derive the power transfer efficiency based on equivalent circuit models representing the BCI test setup. The BCI test is performed on I/O buffers with and without decoupling capacitors, and their immunities are evaluated based on the traditional forward power and the real injected power proposed in this work. The real injected power shows the actual noise power level that the IC can tolerate. Using the real injected power as an indicator for the EMS test, we show that the on-chip decoupling capacitor enhances the EM noise immunity.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.198-206
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• 2013

This paper presents a wide band, fine-resolution digitally controlled oscillator (DCO) with an on-chip 3-D solenoid inductor using the 0.13 ${\mu}m$ digital CMOS process. The on-chip solenoid inductor is vertically constructed by using Metal and Via layers with a horizontal scalability. Compared to a spiral inductor, it has the advantage of occupying a small area and this is due to its 3-D structure. To control the frequency of the DCO, active capacitor and active inductor are tuned digitally. To cover the wide tuning range, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO with solenoid inductor is fabricated in 0.13 ${\mu}m$ process and the die area of the solenoid inductor is 0.013 $mm^2$. The DCO tuning range is about 54 % at 4.1 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The measured phase noise of the DCO output at 5.195 GHz is -110.61 dBc/Hz at 1 MHz offset.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.51 no.2
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• pp.55-60
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• 2002

This paper presents a controller for the multiple DC motors using the CAN(Controller Area Network). The controller has a benefit of reducing the cable connections and making the controller boards compact through the network including expansibility. CAN, among the field buses, is a serial communication methodology which has the physical layer and the data link layer in the ISO's OSI (Open System Interconnect) 7 layered reference model. It provides the user with many powerful features including multi-master functionality and the ability to broadcast / multicast telegrams. When we use a microprocessor chip embedding the CAN function, the system becomes more economical and reliable to react shortly in the data transmission. The controller, we proposed, is composed of two main controllers and a sub controller, which have built with a one-chip microprocessor having CAN function. The sub controller is plugged into the Pentium PC to perform a CAN communication, and connected to the main controllers via the CAN. Main controllers are responsible for controlling two motors respectively. Totally four motors, actuators for the biped robot in our laboratory, are controlled in the experiment. We show that the four motors are controlled properly to actuate the biped robot through the network in real time.

• Journal of Institute of Control, Robotics and Systems
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• v.22 no.8
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• pp.671-677
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• 2016

A Controller Area Network (CAN) is a serial communication protocol that is highly reliable and efficient in many aspects, such as wiring cost and space, system flexibility, and network maintenance. Therefore, it is chosen for the communication protocol between a single chip controller based on Field Programmable Gate Array (FPGA) and peripheral devices. In this paper, the design and implementation of CAN IP, which is written in VHSIC Hardware Description Language (VHDL), is presented. The implemented CAN IP is based on the CAN 2.0A specification. The CAN IP consists of three processes: clock generator, bit timing, and bit streaming. The clock generator process generates a time quantum clock. The bit timing process does synchronization, receives bits from the Rx port, and transmits bits to the Tx port. The bit streaming process generates a bit stream, which is made from a message received from a micro controller subsystem, receives a bit stream from the bit timing process, and handles errors depending on the state of the CAN node and CAN message fields. The implemented CAN IP is synthesized and downloaded into SmartFusion FPGA. Simulations using ModelSim and chip test results show that the implemented CAN IP conforms to the CAN 2.0A specification.