• The Transactions of the Korean Institute of Power Electronics
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• v.23 no.2
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• pp.129-138
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• 2018

Previous single-phase transformerless inverters used active bypass switching circuits that need auxiliary power switches to minimize ground leakage current. However, switching and gate driving losses are increased due to the use of additional power switches. To cope with this drawback, this work proposes a transformerless inverter using a passive bypass filter without any auxiliary power switch. The operation and control of the proposed inverter are described. The ground leakage current characteristics are analyzed for the proposed inverter with the passive bypass filter. The experimental results of the proposed inverter for a 1.0kW prototype system are presented.

• ETRI Journal
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• v.42 no.5
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• pp.773-780
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• 2020

A 40 nm complementary metal oxide semiconductor carrier-aggregated drive amplifier with high linearity is presented for sub-GHz Internet of Things applications. The proposed drive amplifier consists of two high linear amplifiers, which are composed of five differential cascode cells. Carrier aggregation can be achieved by switching on both the driver amplifiers simultaneously and combining the two independent signals in the current mode. The common gate bias of the cascode cells is selected to maximize the output 1 dB compression point (P1dB) to support high-linear wideband applications, and is used for the local supply voltage of digital circuitry for gain control. The proposed circuit achieved an output P1dB of 10.7 dBm with over 22.8 dBm of output 3rd-order intercept point up to 0.9 GHz and demonstrated a 55 dBc adjacent channel leakage ratio (ACLR) for the 802.11af with -5 dBm channel power. To the best of our knowledge, this is the first demonstration of the wideband carrier-aggregated drive amplifier that achieves the highest ACLR performance.

• Journal of IKEEE
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• v.17 no.2
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• pp.119-128
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• 2013

This paper proposes and implements an core transform architecture, which is one of the major processes in HEVC video compression standard. The proposed core transform architecture is implemented with only adders and shifters instead of area-consuming multipliers. Shifters in the proposed core transform architecture are implemented in wires and multiplexers, which significantly reduces chip area. Also, it can process from $4{\times}4$ to $16{\times}16$ blocks with common hardware by reusing processing elements. Designed core transform architecture in 0.13um technology can process a $16{\times}16$ block with 2-D transform in 130 cycles, and its gate count is 101,015 gates.

• Journal of Sasang Constitutional Medicine
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• v.16 no.2
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• pp.114-121
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• 2004

1. Objectives Hyperemesis Gravidarum is one of common symptoms clinically and caused by pregnancy. This is defined as vomiting sufficiently pernicious to produce weight loss, dehydration, acid-base imbalance. In severe case, it also leads to neurologic abnormality including confusion, gate disturbance, nystagmus. We have tried researching effect of herbal medicines, Soyangin Hyungbangsabaek-san. 2. Methods To heal the Hyperemesis Gravidarum, we used Soyangin Hyungbangsabaek-san. 3. Results Hyperemesis Gravidarum of a Soyangin patient was treated with a herb-medicine, and change of her subjective symptom & general condition was managed. 4. Conclusions The constitutional treatment with herb-medicine (Soyangin Hyungbangsabaek-san) was efficacious against Hyperemesis Gravidarum. Further study on management of this disease is needed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.7
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• pp.1369-1373
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• 2003

A linear power amplifier is particularly emphasized on the CDMA system using a linear modulation scheme, because IMD which cause adjacent channel interference and co channel interference is mostly generated in a nonlinear power amplifier. In this paper, a new type of linearization technique proposed. It is presented that balanced MESFET Predistortion linearizer added. Experimental result are present for Korea PCS frequency band. The implemented linearizer is applied to a 30㏈m class A power amplifier for simulation performance. Two-tone signals at 1850 MHz and 1851.23 MHz are injected into the main power amplifier. The main power amplifier with a 12.1㏈ gain and a P1㏈ of 30 ㏈m(two-tone) was utilized. The reduction of IMD is around 22㏈.

• Journal of the Korean Society for Aviation and Aeronautics
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• v.6 no.1
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• pp.147-163
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• 1998

The purpose of this research is to look for the best description of calculating the reasonable Landing Fee. Landing Fee is consisted one of major revenues for maintaining an airport. Traditional Landing Fee Rate has been charged based on the weight factor; Maximum take-off weight, Maximum landing weight, or Maximum authorized weight. To achieve a better reliable value of Landing Fee Rate, The elements of Noise and Peak-Time have to be considered as well as the aircraft weight. This research designs the algorithms for calculating Landing Fee Rate and also Landing Fee, based on the aircraft weight. The Network is also applied to above. That is, CGI(Common Gate Interface) is constructed to interface the terminal of calculating Landing Fee Rate, and the terminal of collecting and transmitting the data such as the Weight. The computer language on the CGI was made by C++ and PERL. The main point of this research is to integrate the airport and Information System and to construct the database which is based on the different perspective of calculating Landing Fee Rate. However, the result of the most efficient and reliable will be computed based on above. This research will broaden the range of application up to the each case of airports.

• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2923-2930
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• 1997

This paper describes two algorithms for technology mapping of multiple output functions into interesting and popular FPGAs (Field Programmable Gate Arrays) that lise look-up table memories. For improvement of technology mapping for FPGA, we use the functional decomposition method for multiple output functions. Two algorithms are proposed. The one is the Roth-Karp algorithm extended for multiple output functions. The other is the novel and efficient algorithm which looks for common decomposition functions through the decomposition procedure. The cost function is used to minimize the number of CLBs and nets and to improve performance of the network. Finally we compare our new algorithm with previous logic design technique. Experimental results show significant reduction in the number of CLBs and nets.

• Journal of Semiconductor Engineering
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• v.2 no.3
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• pp.136-141
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• 2021

This paper analyzes the tree expansion for multiple-input multiple-output (MIMO) detection in the viewpoint of hardware implementation. The tree expansion is to calculate path metrics of child nodes performed in every visit to a node while traversing the detection tree. Accordingly, the tree-expansion unit (TEU), which is responsible for such a task, has been an essential component in a MIMO detector. Despite the paramount importance, the analyses on the TEUs in the literature are not thorough enough. Accordingly, we further investigate the hardware complexity of the TEUs to suggest a guideline for selection. In this paper, we focus on a pair of major ways to implement the TEU: 1) a full parallel realization; 2) a transformation of the formulae followed by common subexpression elimination (CSE). For a logical comparison, the numbers of multipliers and adders are first enumerated. To evaluate them in a more practical manner, the TEUs are implemented in a 65-nm CMOS process, and their propagation delays, gate counts, and power consumptions were measured explicitly. Considering the target specification of a MIMO system and the implementation results comprehensively, one can choose which architecture to adopt in realizing a detector.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.92-94
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• 2019

양방향 스위치를 가지는 Bridgeless PFC 컨버터(BBPFC)는 구조상 복잡한 플로팅 게이트 드라이버를 활용함에도 불구하고 좋은 공통모드 잡음 즉, Common-Mode (CM) 노이즈 특성과 간단한 제어 방법으로 인해 많은 브리지리스 PFC 컨버터 중에서도 고전력 응용분야에서 매우 매력적인 토폴로지이다. 이러한 BBPFC는 도통 경로 상에 위치한 정류 다이오드의 역회복 특성의 상대적인 편차를 활용하여 전력 밀도를 감소시키지 않고도 좋은 공통모드 (CM) 노이즈 특성의 확보가 가능하다. 하지만 이러한 장점을 가지는 BBPFC 구조를 고전력 서버용 전원장치분야에서 활용할 경우, 이미 등록된 특허로 인해 매우 높은 개런티를 지불해야 하므로 그 활용이 매우 제한적이다. 따라서, 본 논문에서는 이미 등록된 특허를 회피하고, 동시에 기존 BBPFC 회로가 가지는 단점인 플로팅 게이트 드라이버를 활용하는 단점을 개선하는 새로운 형태의 브리지리스 PFC 컨버터를 제안한다. 제안된 컨버터는 기존 BBPFC가 가지는 장점인 좋은 (CM) 노이즈 특성을 가지며, 동시에 높은 효율을 달성 할 수 있다. 또한 제안된 컨버터의 경우, 복잡한 플로팅 형태의 게이트 드라이버 회로가 아닌 간단한 부트스트랩 회로를 활용하여 회로를 운용할 수 있다. 더불어 제안된 컨버터는 입력의 양과 음의 주기에서 단 하나의 스위치를 사용하여 회로를 구동할 수 있기 때문에 기존회로 대비 적은 손실을 가져 높은 효율의 획득이 가능하다. 본 논문에서는 제안된 구조에 대해 하이라인 $230V_{RMS}$ 입력과 800W / 400V 출력의 조건을 적용하여 제안하는 구조의 효용성을 검증하고자 한다.

• Journal of the Korean Society of Systems Engineering
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• v.17 no.2
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• pp.49-60
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• 2021

The Core Protection Calculator System (CPCS) is vital for plant safety as it ensures the required Specified Acceptance Fuel Design Limit (SAFDL) are not exceeded. The CPCS generates trip signals when Departure from Nucleate Boiling Ratio (DNBR) and Local Power Density (LPD) exceeds their predetermined setpoints. These setpoints are established based on the operating margin from the analysis that produces the SAFDL values. The goal of this research is to create a simplified CPCS that optimizes operating margin for I-SMRs. Because the I-SMR is compact in design, instrumentation placement is a challenge, as it is with Ex-core detectors and RCP instrumentation. The proposed CPCS addresses the issue of power flux measurement with In-Core Instrumentation (ICI), while flow measurement is handled with differential pressure transmitters between Steam Generators (SG). Simplification of CPCS is based on a Look-Up-Table (LUT) for determining the CEA groups' position. However, simplification brings approximations that result in a loss of operational margin, which necessitates compensation. Appropriate compensation is performed based on the result of analysis. FPGAs (Field Programmable Gate Arrays) are presented as a way to compensate for the inadequacies of current systems by providing faster execution speeds and a lower Common Cause Failure rate (CCF).