• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.6
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• pp.435-443
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• 2017

In this study, we analyzed the effects of the common-gate transistor bias of a switching mode CMOS power amplifier. Although the most earier works occured on the transistor sizes of the cascode structure, we showed that the gate bias of the common-gate transistor also influences the overall efficiency of the power amplifier. To investigate the effect of the gate bias, we analyzed the DC power consumption according to the gate bias and hence the efficiency of the power amplifier. From the analyzed results, the optimized gate bias for the maximum efficiency is lower than the supply voltage of the power amplifier. We also found that an excessively low gate bias may degrade the output power and efficiency owing to the effects of the on-resistance of the cascode structure. To verify the analyzed results, we designed a 1.9 GHz switching mode power amplifier using $0.18{\mu}m$ RF CMOS technology. As predicted in the analysis, the maximum efficiency is obtained at 2.5 V, while the supply voltage of power amplifier is 3.3 V. The measured maximum efficiency is 31.5 % with an output power of 29.1 dBm. From the measureed results, we successfully verified the analysis.

• 한국정보디스플레이학회:학술대회논문집
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• 2000.01a
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• pp.73-74
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• 2000

In recent years, attempts have been made to greatly improve the display quality of active-matrix liquid crystal display devices, and many techniques have been proposed to solve such problems as gate signal delay, feed-through voltage and image sticking[1-3]. To improve these problems which are caused by the feed-through voltage, we have evaluated new driving methods to reduce the feed-through voltage. Two level gate-pulse was used for the gate driving of the cst-on-common structure pixels. These gate driving methods offer better feed-through characteristics than conventional simple gate pulse. Optimized step signal will compensate by step pulse time and voltage. The evaluation of the suggested driving methods were performed by using a TFT-LCD array simulator PDAST which can simulate the gate, data and pixel voltages of a certain pixel at any time and at any location on a TFT array. The effect of the new driving method was effectively analyzed.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.148-150
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• 2009

We have developed 15 inch, 130 blocks local dimming FEL using printed CNT emitters, in which multiple FE blocks were built with a common gate electrode. Cathode electrode formed by the double-metal technique, in which an insulator is interposed between the addressing bus and cathode electrode.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.99-102
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• 1999

In recent years, attempts have been made to greatly improve the display quality of active-matrix liquid crystal display devices, and many techniques have been proposed to solve such problems as gate signal delay, feed-through voltage and image sticking. To improve these problems which are caused by the fried-through voltage, we have evaluated new driving methods to reduce the fled-through voltage. Two level gate-pulse was used for the gate driving of the cst-on-common structure pixels. And two-gate line driving methods with the optimized gate signals were applied for the cst-on-gate structure pixels. These gate driving methods were better feed-through characteristics than conventional simple gate pulse. The evaluation of the suggested driving methods were performed by using a TFT-LCD array simulator PDAST which can simulate the gate, data and pixel voltages of a certain pixel at any time and at any location on a TFT array. The effect of the new driving method was effectively analyzed.

• Journal of the Korean Society for Aviation and Aeronautics
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• v.22 no.3
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• pp.15-23
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• 2014

There have been CFIT(Controlled Flight Into Terrain) accidents that can be prevented if the crew executed go-around. This study is to analyse the common factors of three typical CFIT accidents of Korea in TEM(threat and error management) frame, and the examples of go-around gate and the countermeasures of eight airlines through the survey facilitating go-around to prevent CFIT. The common factors found in three typical CFIT accidents occurred in Korea or by Korean carriers turned out to be in mountainous terrain, in bad weather while in non-precision approach or circling approach by captain as PF(Pilot Flying) when crew make monitoring errors and communication errors. It also turned out that the crew in all three typical tragic CFIT accidents did not execute go-around in unstabilized approaches. The captains did not respond immediately when first officers advised them to go-around until it is too late. Seven out of eight Airlines answered that they use stabilized approach height as 1,000 feet to be stabilized earlier to have more safety margin by enhancing go-around gate regardless of the weather to prevent CFIT in the survey.

• Journal of architectural history
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• v.19 no.2
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• pp.117-132
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• 2010

The Great south gate of Seoul Castle, Sung-Rye-Mun, the east gate of Seoul Castle, Hung-In-Ji-Mun, the south gate of Hwa-Sung Castle, Pal-Dal-Mun and the north gate of Hwa-Sung Castle, Jang-An-Mun are typical significant castle gate of Chosun Dynasty. They have a lot in common with exterior. Additionally there are also something common in dimensions. At first, the arch dimensions of lower story is very similar and the columns of upper story are the regular intervals. Purpose of this study is to confirm similarities above mentioned were intended on purpose and if then what was the reason. The results of this study were described separately as follows. 1. The widths of the arches were based on each 16Cheok and 18Cheok. 2. The heights of the arches followed less strictly rule than the widths. 3. The widths of the arches, 16Cheok was same size as width of middle-size road (中路, Jung-Ro) inside the Castle town in Chosun Dynasty. 4. The widths of the arches, 16Cheok was the standard size of exit went through castle and then the standard size of road arrived at one's destination. 5. The widths of the arches had an effect on the intervals between the columns of the upper story. Finally we recognized that in Chos${\u{o}}$n Dynasty the widths of the gate arches in Seoul castle and Hwa-Sung castle had relevance to the city planning largely and widths of the gate arches had an effect on the intervals between the columns of the upper story partly.

• Journal of architectural history
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• v.18 no.1
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• pp.51-65
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• 2009

The inner gate(The last gate inside a temple, facing the main hall) is not a well-known part in the temple construction of Joseon. This study is focused on seeking truth about the inner gate arrangement of the existing temples as well as proving that it has changed while maintaining a certain relationship with the gate-pavilion arrangement. The inner gate is related to the Cheondo ritual which is letting the dead people's spirits go to heaven, mainly performed in Buddhism, and it has been demonstrated that the inner gate has gradually disappeared as the importance of gate-pavilions has been emphasized along with the changes of the ritual. The inner gate was a common construction before the 18th Century but since that time, it has gradually disappeared and finally it faced the main hall as the gate-pavilion and made the 4 halls-centered arrangement with the temple dormitories on both sides.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.7
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• pp.761-766
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• 2014

This study performs the analytical investigation of the oscillation voltages at the tanks of the series tuned varactor incorporating balanced common-drain, and common-gate Colpitts VCO which are able to work even at the sub-1V power supply voltages. The results the investigation predicts is verified by the simulation on the circuit behaviors of the two VCOs. The analytical investigation finds that the series tuned varactor incorporating balanced common-gate VCO generates greater oscillation voltage at the tank than the series tuned varactor incorporating balanced common-drain VCO does, which in turn is more suitable for generating the low phase noise oscillation signal from the sub-1V supply voltage than the series tuned varactor incorporating balanced common-drain VCO.

• Journal of the Architectural Institute of Korea Planning & Design
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• v.35 no.4
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• pp.45-52
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• 2019

The most ordinary form of residential type in Korea is a plate-type apartment, and the common space in these apartment is attracting as an important factor for enhancing social exchanges among neighbors and forming community consciousness. In addition, it provides a sense of psychological security by enabling natural exchanges and communication in contemporary society. It is desirable to plan the flow of space in such a way that private, semi-private, semi-public, and public spaces are linked. Semi-private and semi-public spaces can be defined as common spaces. Semi-private spaces are strongly recognized in the order of unit household entrance, main entrance, elevator, corridor, staircase, playground, bench, trail, walkway and parking lot, exercise space, main/back gate, the ability to gratify is increased sense of belonging, ownership consciousness formation, defensive function. Semi-public space is strongly recognized in the order of playground, bench, exercise space, trail, main entrance, walkway and parking lot, unit household entrance, main/back gate, corridor, staircase, elevator, the ability to gratify is increase of social contact, Secondary activity space function. In addition, the function to gratify in the common space differs according to gender and age group among resident characteristics, and differs according to corridor type, parking lot type and main entrance type. Therefore, differentiated planning of common space is needed in consideration of these differences in the design of common space in future.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.10 s.352
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• pp.90-97
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• 2006

We report our research work on the millimeter-wave broadband amplifier integrating the shunt peaking technology with the cascode configuration. The millimeter-wave broadband cascode amplifier on MIMIC technology was designed and fabricated using $0.1{\mu}m\;{\Gamma}-gate$ GaAs PHEMT, CPW, and passive library. The fabricated PHEMT has shown a transconductance of 346.3 mS/mm, a current gain cut off frequency ($f_T$) of 113 GHz, and a maximum oscillation frequency ($f_{max}$) of 180 GHz. To prevent oscillation of designed cascode amplifier, a parallel resistor and capacitor were connected to drain of common-gate device. For expansion of the bandwidth and flatness of the gain, we inserted the short stub into bias circuits and the compensation transmission line between common-source device and common-gate device, and then their lengths were optimized. Also, the input and output stages were designed using the matching method to obtain the broadband characteristic. From the measurement, we could confirm to extend bandwidth and flat gain by integrating the shunt peaking technology with the cascode configuration. The cascode amplifier shows the broadband characteristic from 19 GHz to 53.5 GHz. Also, the average gain of this amplifier is about 6.5 dB over the bandwidth.