• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.9
• /
• pp.65-70
• /
• 2008

In FIR filter design, multipliers occupy most of the area. To efficiently reduce the area occupied by multipliers, Common Subexpression Elimination (CSE) algorithm can be used instead of separate multipliers. However, the filter computation time can be increased due to the long carry propagation in CSE circuits. More specifically, when the difference of weights between the two inputs to an adder in CSE circuits is large, long carry propagation time is required due to large sign extension. In this paper, we propose a sign-extension reduction method in common subexpression elimination circuit. By Synopsys simulation using Samsung 0.35um library, it is shown that the proposed method leads to 17%, 31% and 12% reduction in the area, time delay and power consumption, respectively, compared with conventional method.

• ETRI Journal
• /
• v.33 no.5
• /
• pp.695-703
• /
• 2011

The number of adders and critical paths in a multiplier block of a multiple constant multiplication based implementation of a finite impulse response (FIR) filter can be minimized through common subexpression elimination (CSE) techniques. A two-bit common subexpression (CS) can be located recursively in a noncanonic sign digit (CSD) representation of the filter coefficients. An efficient algorithm is presented in this paper to improve the elimination of a CS from the multiplier block of an FIR filter so that it can be realized with fewer adders and low logical depth as compared to the existing CSE methods in the literature. Vinod and others claimed the highest reduction in the number of logical operators (LOs) without increasing the logic depth (LD) requirement. Using the design examples given by Vinod and others, we compare the average reduction in LOs and LDs achieved by our algorithm. Our algorithm shows average LO improvements of 30.8%, 5.5%, and 22.5% with a comparative LD requirement over that of Vinod and others for three design examples. Improvement increases as the filter order increases, and for the highest filter order and lowest coefficient width, the LO improvements are 70.3%, 75.3%, and 72.2% for the three design examples.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.10 no.11
• /
• pp.3087-3093
• /
• 2009

Digital filters are indispensible element in digital signal processing area. The performance of digital filter based on adding and multiplying operation, such as computational speed and power consuming is determined by the orders and coefficients of filter which has on effect area of semiconductor chip when it is implemented by VLSI technology. In this research, in order to performance improvement of digital filter, we proposed the algorithm to speed-up the operation of digital filter associated with the minimum signed digit representation of binary number system and method to simplify the digital filter design associated with common subexpression elimination. The performance of proposed method is evaluated by the computational speed and design-simplicity by experimental implemented digital filter on FPGA.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.3
• /
• pp.40-46
• /
• 1990

This paper describes a design and an implementation of a machine-independent global optimizer which is a required module of RISC compiler system designs. It receives a triple as input and performs data flow analysis, common subexpression elimination and code motion and finally generates the optimized code. Since the implemented optimizer operates on the machine-independent intermediate code, its portability is good for many high level languages and target machines. It performs the effective optimizations to improve the execution time of programs.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.13 no.1
• /
• pp.35-41
• /
• 2020

Fast Fourier transform (FFT) processors have been widely used in various application such as communications, image, and biomedical signal processing. Especially, high-performance and low-power FFT processing is indispensable in OFDM-based communication systems. This paper presents a novel radix-26 FFT algorithm with low computational complexity and high hardware efficiency. Applying a 7-dimensional index mapping, the twiddle factor is decomposed and then radix-26 FFT algorithm is derived. The proposed algorithm has a simple twiddle factor sequence and a small number of complex multiplications, which can reduce the memory size for storing the twiddle factor. When the coefficient of twiddle factor is small, complex constant multipliers can be used efficiently instead of complex multipliers. Complex constant multipliers can be designed more efficiently using canonic signed digit (CSD) and common subexpression elimination (CSE) algorithm. An efficient complex constant multiplier design method for the twiddle factor multiplication used in the proposed radix-26 algorithm is proposed applying CSD and CSE algorithm. To evaluate performance of the previous and the proposed methods, 256-point single-path delay feedback (SDF) FFT is designed and synthesized into FPGA. The proposed algorithm uses about 10% less hardware than the previous algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.12 no.11
• /
• pp.2039-2044
• /
• 2008

The problem of an efficient hardware implementation of multiple constant multiplication is frequently encountered in many digital signal processing applications such as FIR filter and linear transform (e.g., DCT and FFT). It is known that efficient solutions based on common subexpression elimination (CSE) algorithm can yield significant improvements with respect to the area and power consumption. In this paper, we present an efficient specialized adder design method for two common subexpressions ($10{\bar{1}}$, 101) in canonic signed digit (CSD) coefficients. By Synopsys simulations of a radix-24 FFT example, it is shown that the proposed method leads to about 21%, 11% and 12% reduction in the area, propagation delay time and power consumption compared with the conventional methods, respectively.

• Journal of Semiconductor Engineering
• /
• v.2 no.3
• /
• pp.136-141
• /
• 2021

This paper analyzes the tree expansion for multiple-input multiple-output (MIMO) detection in the viewpoint of hardware implementation. The tree expansion is to calculate path metrics of child nodes performed in every visit to a node while traversing the detection tree. Accordingly, the tree-expansion unit (TEU), which is responsible for such a task, has been an essential component in a MIMO detector. Despite the paramount importance, the analyses on the TEUs in the literature are not thorough enough. Accordingly, we further investigate the hardware complexity of the TEUs to suggest a guideline for selection. In this paper, we focus on a pair of major ways to implement the TEU: 1) a full parallel realization; 2) a transformation of the formulae followed by common subexpression elimination (CSE). For a logical comparison, the numbers of multipliers and adders are first enumerated. To evaluate them in a more practical manner, the TEUs are implemented in a 65-nm CMOS process, and their propagation delays, gate counts, and power consumptions were measured explicitly. Considering the target specification of a MIMO system and the implementation results comprehensively, one can choose which architecture to adopt in realizing a detector.