• Journal of the Korean Institute of Telematics and Electronics
• /
• v.19 no.1
• /
• pp.14-19
• /
• 1982

A differential amplifier has been designed and fabricated using aluminum-gate PMOS technology, Only enhaneement-mode MOSFET's are used in the circuit and the dimensions of transistors have been determined using simulation program MSINC. The fabricated integrated circuit with +15V and -l5V power supplies shows an open-loop DC voltage gain of 42 dB, a common mode rejection ratio (CMRR) of 50 dB, and a Power consumption of 20mW.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.6 no.2
• /
• pp.164-172
• /
• 2001

This paper describes common MPPT(Maximum Power Point Tracking) control algorithm; Constant Voltage Control, P&O(Perturbation and Observation), IncCond(Incremental Conductance), and investigated it\`s efficiency. Though simulation and efficiency evaluation, the steady/transient states characteristics and efficiency of control algorithms are analyzed respectively. Also, two-mode MPPT control to improve on the existing control algorithm. Moreover, is proposed for high efficiency this paper suggests a topology for MPPT measuring efficiency and a method of examination.

• Journal of IKEEE
• /
• v.7 no.1 s.12
• /
• pp.72-79
• /
• 2003

Classical designs of optical transimpedance preamplifier for p-i-n photodiode receiver circuits generally employ common source transimpedance input stages. In this paper, we explore the design of a class of current-mode optical transimpedance preamplifier based upon common gate input stages. A feature of current-mode optical transimpedance preamplifier is high gain and high bandwidth. The bandwidth of the transimpedance preamplifier can also be increased by the capacitive peaking technique. In this paper we included the development and application of a circuit analysis technique based on the minimum noise. We develop a general formulation of the technique, illustrate its use on a number of circuit examples, and apply it to the design and optimization of the low-noise transimpedance amplifier. Using the noise minimization method and the capacitive peaking technique we designed a transimpedance preamplifier with low noise, high-speed current-mode transimpedance preamplifier with a 1.57GHz bandwidth, and a 2.34K transimpedance gain, a 470nA input noise current. The proposed preamplifier consumes 16.84mW from a 3.3V power supply.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.17 no.6
• /
• pp.546-552
• /
• 2012

This paper presents an active anti-islanding detection method using negative sequence voltage injection to the grid through a three-phase photovoltaic inverters. Because islanding operation mode can cause a variety of problems, the islanding detection of grid-connected photovoltaic inverter is the mandatory feature. The islanding mode is detected by measuring the magnitude of negative sequence impedance calculated by the negative sequence voltage and current at the point of common coupling. Simulation and experimental test are performed to verify the effectiveness of the proposed method which can detect the islanding mode in the specified time. The test has been done in accordance with the condition on IEEE Std 929-2000.

• Journal of Korea Society of Industrial Information Systems
• /
• v.18 no.5
• /
• pp.15-18
• /
• 2013

This paper presents an analog front-end for electroencephalogram(EEG) signal processing. Since EEG signals are typically weak and located at very low frequencies, it is imperative to implement an amplifier with high gain, high common-mode rejection ratio(CMRR) and good noise immunity at very low frequencies. The analog front-end of this paper consists of a programmable-gain instrumentation amplifier and a band-pass filter. A frequency chopping technique is employed to remove the low-frequency noise. The circuits were fabricated in 0.18um CMOS technology and measurements showed that the analog front-end has the maximum gain of 60dB and >100dB CMRR over the programmable gain range.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.6 s.360
• /
• pp.19-27
• /
• 2007

This paper presents power supply-insensitive Gbps low power LVDS I/O circuits. The proposed LVDS I/O has been designed and simulated using 1.8V, $0.18\;{\mu}m$ TSMC CMOS Process. The LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and an output stage with the switched capacitor common mode feedback(SC-CMFB). The differential phase splitter generates a pair of differential signals which provides a balanced duty $cycle(50{\pm}2%)$ and phase difference$(180{\pm}0.2^{\circ})$ over a wide supply voltage range. Also, $V_{OD}$ voltage is 250 mV which is the smallest value of the permissible $V_{OD}$ range for low power operation. The output buffer maintains the required $V_{CM}$ within the permissible range$(1.2{\pm}0.1V)$ due to the SC-CMFB. The receiver covers a wide input DC offset $range(0.2{\sim}2.6\;V)$ with 38 mV hysteresis and Produces a rail-to-rail output over a wide supply voltage range. Beside, the designed receiver has 38.9 dB gain at 1 GHz, which is higher than conventional receivers.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.12
• /
• pp.82-90
• /
• 2011

A novel class AB current subtracter(CS) and its application to Norton amplifier(NA) for low-power current-mode signal processing are designed. The CS is composed of a translinear cell, two current mirrors, and two common-emitter(CB) amplifiers. The principle of the current subtraction is that the difference of two input current applied translinear cell get from the current mirror, and then the current amplify through CB amplifier with ${\beta}$ times. The NA is consisted of the CS and wideband voltage buffer. The simulation results show that the CS has current input impedance of $20{\Omega}$, current gain of 50, and current input range of $i_{IN1}$ > $i_{IN2}{\geq}4I_B$. The NA has unit gain frequency of 312 MHz, transresistance of 130 dB, and power dissipation of 4mW at ${\pm}2.5V$ supply voltage.

• Journal of IKEEE
• /
• v.18 no.2
• /
• pp.220-227
• /
• 2014

This paper presents a control method of Single-Inductor Dual-Output DC-DC Converter using Common mode feedback and differential feedback loops. To generate duty used for differential mode feedback loop, this paper propose relative sawtooth circuit using current divider circuit which makes ramp signal with variable dead-time. Two outputs of the Single-Inductor Dual-Output DC-DC Converter are specified for 2.8 V and 4.2 V with input voltage 2.5 V. The maximum conversion efficiency of designed SIDO DC-DC Converter is 95% at total output power of 539mW. Cross regulations of Boost1 and Boost2 are 3.57% and 4% each, when increasing twice times output current.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.2
• /
• pp.22-28
• /
• 1998

A $g_m$-control technique using a new electronic zener diode (EZD) for CMOS rail-torail input stages is presented. A regulated CMOS inverter is used as an EZD to obtain a constant-$g_m$ input stage. The turn-off characteristic of the proposed EZD is better than that of the existing EZD using two complementarey diodes, and thus, better $g_m$-control can be achieved. With this input stage, a 3V constant-$g_m$ rail-to-rail CMOS op-amp has been designed and fabricated using a $0.8\mu\extrm{m}$single-poly, double-metal CMOS process. Measurements results show that the $g_m$ variation is about 6% over the entire input common-mode range, and the op-amp has a dc gain of 88dB and a unity-gain frequency of 4MHz for $C_L=20pF, R_L=10k\Omega$

• Proceedings of the KIEE Conference
• /
• 2001.11c
• /
• pp.348-351
• /
• 2001

In this paper, the Gm-C filter for low voltage and low power applications using a fully-differential transconductor is presented. The designed transconductor using the series composite transistors and the low voltage composite transistors has wide input range at low supply voltage. A negative resistor load (NRL) technology for high DC gain of the transconductor is employed with a common mode feedback(CMFB). As a design example, the third-order Elliptic lowpass filter is designed. The designed filter is simulated and examined by HSPICE using TSMC $0.35{\mu}m$ CMOS n-well parameters. The simulation results show 138kHz cutoff frequency and 11.05mW power dissipation with a 3.3V supply voltage.