• Proceedings of the KIEE Conference
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• 2007.11a
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• pp.173-174
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• 2007

본 논문에서는 scan 전극과 common 전극 사이에 보조 전극을 가진 PDP에서 asymmetry, long gap mode 와 같은 새로운 구동방법을 제안한다. asymmetry mode에서 주전극의 가운데 부분에 위치한 보조전극은 리셋, 어드레스, 서스테인의 모든 구간동안 scan 또는 common 전극에 연결되어 있다. long gap mode에서는 전기적으로 끊어져있거나 초기 몇 개의 서스테인 펄스를 제외하고 서스테인 구간동안 Vs/2의 전압으로 유지된다. 제안된 조와 구동 방법에서 전력에너지소비를 최소화함으로써 더 높은 발광효율을 얻을 수 있다. 새로운 구동방법의 효용은 다양한 Xe분압상태에서도 연구되었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.1
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• pp.68-79
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• 1992

In the high speed analog system satellite communication system, video signal processing and optical fiber interface circuits, GaAs high gain operational amplifier is advantageous due to obtain a high gain because of its low transconductance and other drawbacks, such as low frequency dispersion and process variation. Therefore in this paper, a circuit techniques for improving the voltage gain for GaAs MESFET amplifier is presented. Also, various types of existing current mirror and current mirror proposed are compared.To obtain the high differential gain, bootstrap gain enhancement technique is used and common mode feedback is employed in differential amplifier.The simulation results show that gain is higher than that of basic amplifier about 18.6dB, and stability and frequency performance of differential amplifier are much improved.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.111-117
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• 2006

Reconfigurable CMOS low-noise amplifier (LAN) has been developed for multi-mode/multi-band wireless receiver. By employing common-gate input stage, the performance can be optimized for multiple operation bands by simply controlling the output load impedance. Although the conventional common-gate LAN has larger than 3dB noise figure (NF), the newly developed negative feedback scheme enables the common-gate input LNA to have less than 2dB NF. To have optimum linearity performance of wireless receiver, the gain of the LNA can be controlled. The LNA implemented in a 0.13mm CMOS technology shows $19{\sim}20dB$ voltage gain, $1.7{\sim}2.0dB$ NF, -2dBm iIP3 at $1.8{\sim}2.5GHz$ frequency range. The LNA dissipates 7mW from a 1.2V supply voltage.

• Proceedings of the KIPE Conference
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• 2017.11a
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• pp.9-10
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• 2017

본 논문은 MMC 토플로지에서 EMI 노이즈와 누설 전류를 발생시키는 커먼모드 전압(Commom Mode Voltage, CMV)을 스위칭 스테이트 해석을 통해 일반화 하고 이를 저감할 수 있는 기법을 제안한다. 이러한 CMV에 관한 해석과 저감 기법은 시뮬레이션으로 타당성을 검증하였다.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.638-642
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• 2005

This paper proposes a modified space-vector pulse width modulation (PWM) strategy which can restrict the common-mode voltage for three-phase to three-phase matrix converter and still keep sinusoidal input and output waveforms and unity power factor at the input side. The proposed control method has been developed based on contributing the appropriate space vectors instead of using zero space vectors. The advantages of this proposed method is to reduce the peak value of common-mode voltage to 42% beside the lower high harmonic components as compared to the conventional SVM method. Hence, the new table is also presented with the new space vector rearrangement. Furthermore, the voltage transfer ratio is unaffected by the proposed method. A simulation of the overall system has been carried out to validate the advantages of the proposed method.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.390-391
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• 2018

본 논문은 직류단 전원을 공유하는 복수의 인버터로 구성된 시스템에서 EMI 저감을 위한 연동제어 PWM 생성 기법을 제안한다. PWM 제어에 의한 스위칭시 전력단 중성점에서 커먼모드 전압이 생성되고, 기생 캐패시터를 통해 전원라인으로 유입되어 EMI 노이즈가 발생된다. 복수의 인버터 시스템에서도 동일한 현상이 나타나고, 이로인한 불특정한 커먼모드 전류가 발생한다. 본 논문에서는 2개의 인버터를 PWM 시점의 동기제어를 통해 커먼모드 노이즈를 상쇄하고자한다. 제안한 제어 기법을 검증하기 위하여 시뮬레이션으로 분석하며, 간이 실험 통해 검증한다.

• The Transactions of the Korean Institute of Power Electronics
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• v.28 no.1
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• pp.1-7
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• 2023

A grid-connected 3-level NPC inverter is a power conversion device that connects renewable energy generators, such as photovoltaic or wind turbines to the grid. Although many studies have focused on this inverter, commercializing it requires strictly satisfying various safety and power quality-related standards. Among many standards, leakage current and grid current total harmonic distortion(THD) can be affected by external factors such as installation environment, aging, and grid conditions. Hence, inverter operations that can satisfy these standards need to be explored. In this study a 3-level NPC inverter operation algorithm using the Phase Opposition Disposition-PWM method that can effectively reduce leakage current and switching frequency adjustment to reduce THD effectively has been proposed.

• Journal of IKEEE
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• v.22 no.4
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• pp.1006-1011
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• 2018

This paper proposes a three level buck converter utilizing multi-bit flying capacitor voltage control. The conventional three-level buck converter can not control the flying capacitor voltage, so that the operation is unstable or the circuit for controlling the flying capacitor voltage can not be applied to the PWM mode. Also when the load current is increased, an error occurs in the inductor voltage. The proposed structure can control the flying capacitor voltage in PWM mode by using differential difference amplifier and common mode feedback circuit. In addition, this paper proposes a 3bit flying capacitor voltage control circuit to optimize the operation of the three level buck converter depending on the load current, and a triangular wave generation circuit using the schmitt trigger circuit. The proposed 3-level buck converter is designed in $0.18{\mu}m$ CMOS process and has an input voltage range of 2.7V~3.6V and an output voltage range of 0.7V~2.4V. The operating frequency is 2MHz, the load current range is 30mA to 500mA, and the output voltage ripple is measured up to 32.5mV. The measurement results show a maximum power conversion efficiency of 85% at a load current of 130 mA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.60-68
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• 2007

A technique is presented to extract differential second harmonic output from common source nodes of a cross-coupled P-& N-FET oscillator. Provided the impedances at the common source nodes are optimized and the fundamental swing at the VCO core stays in a proper mode, it is found that the amplitude and phase errors can be kept within $0{\sim}1.6dB$ and $+2.2^{\circ}{\sim}-5.6^{\circ}$, respectively, over all process/temperature/voltage corners. Moreover, an impedance-tuning circuit is proposed to compensate any unexpectedly high errors on the differential signal output. A Prototype 5-GHz VCO with a 2.5-Hz LC resonator is implemented in $0.18-{\mu}m$ CMOS. The error signal between the differential outputs has been measured to be as low as -70 dBm with the aid of the tuning circuit. It implies the push-push outputs are satisfactorily differential with the amplitude and phase errors well less than 0.34 dB and $1^{\circ}$, respectively.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.386-387
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• 2019

본 논문에서는 단상 컨버터/3상 인버터 시스템에서 공통모드에 의한 누설전류를 분석하였다. 컨버터/인버터 시스템의 공통모드 전압은 시스템에 존재하는 기생 임피던스를 충방전함으로써 수 A의 누설전류를 발생시킨다. 이에 본 논문에서는 단상 컨버터/3상 인버터 시스템에서 컨버터 입력 측 변압기와 전동기의 기생 임피던스를 고려하여 누설전류를 분석하였으며, 누설전류를 감소하기 위해 공통모드 전압 저감하는 방법을 제안한다. 모의실험을 통하여 제안된 기법에 의한 누설전류의 저감효과를 확인하였다.