• The Transactions of the Korean Institute of Electrical Engineers
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• v.34 no.7
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• pp.289-296
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• 1985

The Townsend primary ionization coefficient a was measured by the luminous-flux method using the fact that the intensity of radiant light is proportional to electron density in the townsend discharge domain. The ranges of measurements were 15for He gas and 10

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.3
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• pp.510-520
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• 2011

In this paper, we propose a new multiplication algorithm for primitive polynomial with all 1 of coefficient in case that m is odd and even on finite fields $GF(3^m)$, and compose the multiplier with parallel input-output module structure using the presented multiplication algorithm. The proposed multiplier is designed $(m+1)^2$ same basic cells that have a mod(3) addition gate and a mod(3) multiplication gate. Since the basic cells have no a latch circuit, the multiplicative circuit is very simple and is short the delay time $T_A+T_X$ per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.

• Journal of the Korea Society of Computer and Information
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• v.18 no.2
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• pp.9-17
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• 2013

In this paper, we propose a new multiplication algorithm for two polynomials using primitive polynomial with all 1 of coefficient on finite fields GF($2^m$), and design the multiplier with high-speed parallel input-output module structure using the presented multiplication algorithm. The proposed multiplier is designed $m^2$ same basic cells that have a 2-input XOR gate and a 2-input AND gate. Since the basic cell have no a latch circuit, the multiplicative circuit is very simple and is short the delay time $D_A+D_X$ per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.

• Journal of the Chungcheong Mathematical Society
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• v.33 no.4
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• pp.489-495
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• 2020

We define new integral operators on the Haydy space similar to Szegö projection. We consider a relationship between these Szegö type operators and the partial sum of Taylor series on the Hardy space.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.10
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• pp.1403-1408
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• 2021

Recently, FPGA-based AI processors are being studied actively. Deep convolutional neural networks (CNN) are basic computational structures performed by AI processors and require a very large amount of multiplication. Considering that the multiplication coefficients used in CNN inference operation are all constants and that an FPGA is easy to design a multiplier tailored to a specific coefficient, this paper proposes a methodology to optimize the multiplier. The method utilizes 2's complement and distributive law to minimize the number of bits with a value of 1 in a multiplication coefficient, and thereby reduces the number of required stacked adders. As a result of applying this method to the actual example of implementing CNN in FPGA, the logic usage is reduced by up to 30.2% and the propagation delay is also reduced by up to 22%. Even when implemented with an ASIC chip, the hardware area is reduced by up to 35% and the delay is reduced by up to 19.2%.

• Journal of Korean Society of Water and Wastewater
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• v.25 no.2
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• pp.185-192
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• 2011

Pearson's correlation was used to determine relations between infiltration and affecting factors using flow monitoring data measured in 24 areas with different characteristics. Factors showed relatively high correlations than others were indexed to determine infiltration rates of the study area. Among 8 factors(service area, sewer length, sewer diameter, multiplier of sewer length and diameter, number of manholes, population, number of properties, number of households) tested, the multiplier of sewer length and diameter, the number of population and the number of household in each service area indicated higher correlation coefficient(>0.8) than others. The goodness of fitness of linear regressions between infiltration and the factors followed the order: sewer length and diameter(0.68)> population(0.65)> number of household(0.60). Infiltration rates calculated by the multiplier of sewer length and diameter, the number of population and the number of household in each service area were 0.046~1.0396 $m^{3}/d{\cdot}mm-km$, 0.0917~1.7355 $m^{3}/capita{\cdot}d$, 0.196~4.529 $m^{3}/household {\cdot}d$ respectively. After sewerage rehabilitation work of the area, the infiltration rates calculated by above factors with high correlations are expected to be used for comparing effectiveness of the work once they are estimated under the same flow measuring conditions.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.2
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• pp.139-144
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• 2011

The modern digital logic technology does not yet satisfy the speed requirements of real-time DSP circuits due to synchronized operation of multiplication and accumulation. This operation degrades DSP performance. Therefore, the double-base number system (DBNS) has emerged in DSP system as an alternative methodology because of fast multiplication and hardware simplicity. In this paper, authors propose a novel multiplication architecture. One operand is an output of a flash analog-to-digital converter (ADC) in DBNS format, while the other operand is a coefficient in the IEEE standard floating-point number format. The DBNS digital output from ADC is produced through a new double base number encoder (DBNE). The multiplied output is in the format of the IEEE standard floating-point number (FPNS). The proposed circuits process multiplication and conversion together. Compared to a typical multiplier that uses the FPNS, the proposed multiplier also consumes 45% less gates, and 44% faster than the FPNS multiplier on Spartan-3 FPGA board. The design is verified with FIR filter applications.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.37 no.1
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• pp.9-18
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• 2013

Two-phase vapor-liquid flows exist in many shell and tube heat exchangers such as condensers, evaporators, and nuclear steam generators. To understand the fluid dynamic forces acting on a structure subjected to a two-phase flow, it is essential to obtain detailed information about the characteristics of a two-phase flow. The characteristics of a two-phase flow and the flow parameters were introduced, and then, an experiment was performed to evaluate the pressure loss in the tube bundles and the fluid-dynamic force acting on the cylinder owing to the pressure distribution. A two-phase flow was pre-mixed at the entrance of the test section, and the experiments were undertaken using a normal triangular array of cylinders subjected to a two-phase cross-flow. The pressure loss along the flow direction in the tube bundles was measured to calculate the two-phase friction multiplier, and the multiplier was compared with the analytical value. Furthermore, the circular distributions of the pressure on the cylinders were measured. Based on the distribution and the fundamental theory of two-phase flow, the effects of the void fraction and mass flux per unit area on the pressure coefficient and the drag coefficient were evaluated. The drag coefficient was calculated by integrating the measured pressure on the tube by a numerical method. It was found that for low mass fluxes, the measured two-phase friction multipliers agree well with the analytical results, and good agreement for the effect of the void fraction on the drag coefficients, as calculated by the measured pressure distributions, is shown qualitatively, as compared to the existing experimental results.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.101-104
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• 2002

This paper propose that is algorithm of power dissipation reduction in the high level synthesis design for DSP(Digital Signal Processor), as the portable terminal system recently demand high power dissipation. This paper obtain effect of power dissipation reduction and switching activity that increase correlation of operands as input data of function unit. The algorithm search loop or repeatedly data to the input operands of function unit. That can be reduce the power dissipation using the new low power high level synthesis algorithm. In this Paper, scheduling operation search same nodes from input DFG(Data Flow Graph) with correlation coefficient of first input node and among nodes. Function units consist a multiplier, an adder and a register. The power estimation method is added switching activity for each bits of nodes. The power estimation have good efficient using proposed algorithm. This paper result obtain more Power reduction of fifty percents after using a new low power algorithm in a function unit as multiplier.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.711-714
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• 2000

In this paper, we propose a high-speed multiplier-free realization using ROM’s to store the results of coefficient scalings in Combination With higher signal rate and pipelined operations. We show that hardware multipliers are not needed. By varying some parameters, the proposed structure provides various combinations of hardware and clock speed (or through-put). An example is given comparing the proposed realization with the distributed arithmetic (DA) realization. Results show that With Proper Choices of the Parameters the proposed structure achieves a faster processing speed with less hardware, as compared to the DA realization.