• Title/Summary/Keyword: Code Information Check

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Adaptive Decision Feedback Equalizer Based on LDPC Code for the Phase Noise Suppression and Performance Improvement (위상잡음 제거와 성능향상을 위한 LDPC 부호 기반의 적응형 판정 궤환 등화기)

  • Kim, Do-Hoon;Ryu, Heung-Gyoon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.37 no.3A
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    • pp.179-187
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    • 2012
  • In this paper, we propose an adaptive DFE (Decision Feedback Equalizer) based on LDPC (Low Density Parity Check) code for phase noise suppression and performance improvement. The proposed equalizer in this paper is applied for wireless repeater system. So as to meet ever increasing requirements on higher wireless access data rate and better quality of service (QoS), the wireless repeater system has been studied. The echo channel and RF impairments such as phase noise produce performance degradation. In order to remove echo channel and phase noise, we suggest a novel adaptive DFE equalizer based on LDPC code. The proposed equalizer helps to compensate RF impairments and improve the performance significantly better than used independently. In addition, proposed equalizer has less iteration number of LDPC code. So, the proposed equalizer system has low complexity.

A Multi-mode LDPC Decoder for IEEE 802.16e Mobile WiMAX

  • Shin, Kyung-Wook;Kim, Hae-Ju
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.1
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    • pp.24-33
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    • 2012
  • This paper describes a multi-mode LDPC decoder which supports 19 block lengths and 6 code rates of Quasi-Cyclic LDPC code for Mobile WiMAX system. To achieve an efficient implementation of 114 operation modes, some design optimizations are considered including block-serial layered decoding scheme, a memory reduction technique based on the min-sum decoding algorithm and a novel method for generating the cyclic shift values of parity check matrix. From fixed-point simulations, decoding performance and optimal hardware parameters are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 380,000 gates and 52,992 bits RAM, and the estimated throughput is about 164 ~ 222 Mbps at 56 MHz@1.8 V.

Architecture of an LDPC Decoder for DVB-S2 using reuse Technique of processing units and Memory Relocation (연산기와 메모리 재사용을 이용한 효율적인 DVB-S2 규격의 LDPC 복호기 구조)

  • Park Jae-Geun;Lee Chan-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.9 s.351
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    • pp.31-37
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    • 2006
  • Low-density parity-check (LDPC) codes are recently emerged due to its excellent performance. The standard for European high definition satellite digital video broadcast, DVB-S2 has adopted LDPC codes as a channel coding scheme. This paper proposes a DVB-S2 LDPC decoder architecture using a hybrid parity check matrix which is efficient in hardware implementation for both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the hybrid H-matrix scheme, the architecture of LDPC decoder for DVB-S2 can be very practical and efficient. In addition, we show a new Variable Node processor Unit (VNU) architecture to reuse the VNU for various code rates and optimized block memory placement to reuse. We design a DVB-S2 LDPC decoder of code rate 1/2 usng the proposed architecture. We estimate the performance of the DVB-S2 LDPC decoder and compare it with other decoders.

A new syndrome check error estimation algorithm and its concatenated coding for wireless communication

  • 이문호;장진수;최승배
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.22 no.7
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    • pp.1419-1426
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    • 1997
  • A new SCEE(Syndrome Check Error Estimation) decoding method for convolutional code and concatenated SCEE/RS (Reed-Solomon) conding scheme are proposed. First, we describe the operation of the decoding steps in the proposed algorithm. Then deterministic values on the decoding operation are drived when some combination of predecoder-reencoder is used. Computer simulation results show that the compuatational complexity of the proposed SCEE decoder is significantly reduced compared to that of conventional Viterbi-decoder without degratation of the $P_{e}$ performance. Also, the concatenated SCEE/RS decoder has almost the same complexity of a RS decoder and its coding gain is higher than that of soft decision Viterbi or RS decoder respectively.

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Analysis of error correction capability and recording density of an optical disc system with LDPC code (LDPC 코드를 적용한 광 디스크 시스템의 에러 정정 성능 및 기록 용량 분석)

  • 김기현;김현정;이윤우
    • Proceedings of the IEEK Conference
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    • 2003.11a
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    • pp.537-540
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    • 2003
  • In this paper, we evaluated error correction performance and recording density of an optical disc system. The performance of Low-Density Parity Check code (LDPC) is compared to the HD-DVD (BD) ECC. The recording density of optical disc can be increased by reducing the redundancy of the user data. Moreover, since the correction capability of LDPC with decreased redundancy is better than that of BD, the recording density can also be increased by reducing the mark length of the data on the disc surface.

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Row-splitting Algorithm for Low Density Parity Check Codes (LDPC 부호를 위한 행 분할 알고리즘)

  • Jung, Man-Ho;Lee, Jong-Hoon;Kim, Soo-Young;Song, Sang-Seob
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.45 no.2
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    • pp.92-96
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    • 2008
  • Practical communication systems need to operate at various different rates. This paper describes and analyzes low-density parity check codes for various different rates. From a specific mother code, it allows LDPC codes for different rate. The advantage of this technique is that each different rate LDPC codes have a same block length as mother code though the rate changes so it can make up for the weak points of puncturing and shortening which reduce their block length as the rate changes. Row-splitting method is to split the row, so that the rate changes from a higher rate to lower rate and cause of its own property, it can overcome the defect of row-combining method.

Nonbinary Multiple Rate QC-LDPC Codes with Fixed Information or Block Bit Length

  • Liu, Lei;Zhou, Wuyang;Zhou, Shengli
    • Journal of Communications and Networks
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    • v.14 no.4
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    • pp.429-433
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    • 2012
  • In this paper, we consider nonbinary quasi-cyclic low-density parity-check (QC-LDPC) codes and propose a method to design multiple rate codes with either fixed information bit length or block bit length, tailored to different scenarios in wireless applications. We show that the proposed codes achieve good performance over a broad range of code rates.

A Code Concealment Method using Java Reflection and Dynamic Loading in Android (안드로이드 환경에서 자바 리플렉션과 동적 로딩을 이용한 코드 은닉법)

  • Kim, Jiyun;Go, Namhyeon;Park, Yongsu
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.25 no.1
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    • pp.17-30
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    • 2015
  • Unlike existing widely used bytecode-centric Android application code obfuscation methodology, our scheme in this paper makes encrypted file i.e. DEX file self-extracted arbitrary Android application. And then suggests a method regarding making the loader app to execute encrypted file's code after saving the file in arbitrary folder. Encrypted DEX file in the loader app includes original code and some of Manifest information to conceal event treatment information. Loader app's Manifest has original app's Manifest information except included information at encrypted DEX. Using our scheme, an attacker can make malicious code including obfuscated code to avoid anti-virus software at first. Secondly, Software developer can make an application with hidden main algorithm to protect copyright using suggestion technology. We implement prototype in Android 4.4.2(Kitkat) and check obfuscation capacity of malicious code at VirusTotal to show effectiveness.

A Study on the Improved Parity Check Receiver for the Extended m-sequence Based Multi-code Spread Spectrum System with Code Set Partitioning and Constant Amplitude Precoding (코드집합 분할 방식의 확장 m-시퀀스 기반 정진폭 멀티코드 대역확산 통신 시스템을 위한 개선된 패리티 검사 기반 수신기에 관한 연구)

  • Han, Jun-Sang;Kim, Dong-Joo;Kim, Myoung-Jin
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.49 no.8
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    • pp.1-11
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    • 2012
  • The multi-code spread spectrum communication system, which spreads data bit stream by multiplexing orthogonal codes, can transmit data in high rate. However it needs the high-cost good linear amplifier because of the multi-level output signal. In order to overcome this drawback several systems making the amplitude of output signal constant with Walsh codes have been proposed. Recently constant amplitude pre-coded multi-code spread spectrum systems using extended m-sequence have been proposed. In this paper we consider an extended m-sequence based constant amplitude multi-code spread spectrum system with code set partitioning. By grouping the orthogonal codes into 4 subsets, not only is the computational complexity of the transceiver reduced but BER performance also improves. It has been shown that parity checking on four detected codes at the receiver can correct code detection error and result in BER performance enhancement. In this paper we propose a improved parity check receiver. We carried out computer simulation to verify feasibility of the proposed algorithm.

A performance analysis of LDPC decoder for IEEE 802.16e WiMAX System (IEEE 802.16e WiMAX용 LDPC 복호기의 성능분석)

  • Kim, Eun-Suk;Kim, Hae-Ju;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2010.10a
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    • pp.722-725
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    • 2010
  • In this paper, BER performance and error convergence speed of layered LDPC(Low Density Parity Check) decoder which supports IEEE 802.16e WiMAX standard is analyzed, and optimal design conditions for hardware implementation are derived. A LDPC decoder is modeled and simulated at AWGN channel with QPSK modulation by Matlab. The parity check matrix(PCM) for IEEE 802.16e standard which has block lengths of 576, 1440, 2304 and code rates of 1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6 are used. Fixed-point simulation results show that fixed-point bit-width should be more than 8 bits for acceptable decoding performance.

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