• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.7
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• pp.38-45
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• 2006

The superconducting fault current limiters(SFCLs) provide the effect such as enhancement in power system reliability due to limiting the fault current within a few miliseconds. Among various SFCLs we have developed a flux-lock type SFCL and exploited a special design to effectively reduce the fault current according to properly adjustable magnetic field after the short-circuit test. This SFCL consists of two copper coils wound in parallel on the same iron core and a component using the YBCO thin film connected in series to the secondary copper coil. Meanwhile, operating characteristics can be controlled by adjusting the inductances and the winding directions of the coils. To analyze the operational characteristics, we compared closed-loop with open-loop iron core. When the applied voltage was 200[Vrms] in the additive polarity winding, the peak values of the line current the increased up to 30.71[A] in the closed-loop and 32.01[A] in the open-loop iron core, respectively. On the other hand, in the voltages generated at current limiting elements were 220.14[V] in the closed-loop and 142.73[V] in the opal-loop iron core during first-half cycle after fault instant under the same conditions. We confirmed that the open-loop iron core had lower power burden than in the closed-loop iron core. Consequently, we found that the structure of iron core enabled the flux-lock type SFCL at power system to have the flexibility.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.152-156
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• 2013

This paper presents a fast-lock dual-loop successive approximation register-controlled duty-cycle corrector (SARDCC) circuit using a mixed (binary+sequential) search algorithm. A wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy have been achieved by utilizing the dual-loop architecture and the binary search SAR that achieves the fast duty-cycle correcting property. By transforming the binary search SAR into a sequential search counter after the first DCC lock-in, the proposed dual-loop SARDCC keeps the closed-loop characteristic and tracks variations in process, voltage, and temperature (PVT). The measured duty cycle error is less than ${\pm}0.86%$ for a wide input duty-cycle range of 15-85 % over a wide frequency range of 0.5-2.0 GHz. The proposed dual-loop SARDCC is fabricated in a 0.18-${\mu}m$, 1.8-V CMOS process and occupies an active area of $0.075mm^2$.

• Journal of Power Electronics
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• v.10 no.5
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• pp.468-476
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• 2010

This paper proposes and develops a new direct voltage control (DVC) approach. This method is designed to be applied in various applications for AC drives fed with a three-phase voltage source inverter (VSI) working with a constant switching time interval as in the standard direct torque control (DTC) scheme. Based on a very strong min(max) criterion dedicated to selecting the inverter voltage vector, the developed DVC scheme allows the generation of accurate voltage forms of waves. The DVC algorithm is implemented on a dSPACE DS1104 controller board and then compared with the space vector pulse width modulation technique (SVPWM) in an open loop AC drive circuit. To demonstrate the efficiency of the developed algorithm in real time and in closed loop AC drive applications, a scalar control scheme for induction motors is successfully implemented and experimentally studied. Practical results prove the excellent performance of the proposed control approach.

• Journal of Biosystems Engineering
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• v.25 no.4
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• pp.273-278
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• 2000

The hybrid heat pump system of the air to air and / or air to water was composed and its COP was analyzed with the ambient temperature on the opened and closed loop system respectively. The results be indicated by the equation(7) that the COP(Coefficient of Performance) of air-source(air to air and / or air-water) heat pump is effected with the ambient air temperature and AVACTHE.(Automatic Variable Area Capillary Type Heat Exchanger) 2. The COP of air-to-water heat pump without AVACTHE decreased in accordance with the ambient temperature decrease, however in case of the heat pump with AVACTHE the COP was maintained at 2.8∼3.0 level when the ambient temperature decrease from -$5^{\circ}C$ to $-11^{\circ}C$. 3. The COP of the air-to-water heat pump operated on the open loop was higher 40∼58% than that of the heat pump operated on the close loop. 4. The lower ambient temperature air effect on the COP of the air-to-air heat pump operated on the semi closed loop could be controlled using the AVACTHE, and at the high ambient air temperature the COP increased using the Bypass circuit.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.68-77
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• 2003

An improved negative capacitance circuit that cancels out input impedance of a front-end in a bioimpedance measurement and operates stably with a low gain margin has been proposed. Since the proposed circuit comprises wide-band operational amplifiers, selecting operational amplifiers is easy, while an operational amplifier of prefer bandwidth should be chosen to apply conventional circuit. Also, since gain margin can be controlled by a feedback resistor connected serially with a feedback capacitor, gain margin is tuneable with a potentiometer. The input impedance of the proposed circuit is two times larger than that of the conventional circuit and 40-times than that without a negative capacitance circuit. Furthermore, closed-loop phase response of the proposed circuit is better than that of the conventional circuit or without a negative capacitance circuit. Above all, for the proposed circuit, the frequency at which a gain peaking occurs is higher than the frequency at which the loop gain becomes a maximum. Thus, the proposed circuit is not affected by a gain peaking and can be operated with a very low gain margin.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.4
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• pp.235-242
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• 2003

In this paper, a fuzzy controller is designed to suppress and stabilize the chaotic behavior of Chua's circuit. This controller is constructed by the following two phases. First, Chua's circuit is represented by an affine fuzzy model. Second, a fuzzy controller is designed so that the stability of the closed-loop system composed of the fuzzy controller and the affine fuzzy model of Chua's circuit is rigorously guaranteed. The stability condition of the affine fuzzy system is derived and is recast in the formulation of linear matrix inequalities. The guaranteed stability is global and asymptotic. Finally, the applicability of the suggested methodology is highlighted via computer simulations.

• The Transactions of the Korean Institute of Power Electronics
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• v.3 no.3
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• pp.231-239
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• 1998

This paper presents the dynamic analysis and control loop design of a zero voltage switching full bridge (ZVS-FB) PWM DC/DC converter. The small-signal model is derived incorporating the effects of phase shift control and the utilization of transformer leakage inductance and power FET junction capacitance to achieve zero voltage resonant switching. These effects are modeled by introducing additional feedforward and feedback terms for duty cycle modulation. Based on the results of the small-signal analysis, the control loop is designed using a simple two-pole one-zero compensation circuit. To show the validity of the design procedures, the small signal analysis of the closed loop system is carried out and the potential of the zero voltage switching and the superiority of the dynamic characteristics are verified through the experiment with a 2 kW prototype converter.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.12 s.91
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• pp.1161-1167
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• 2004

The conventional PLL(phase locked loop) frequency synthesizer takes a long switching time because of the inherent closed-loop structure. The digital hybrid PLL(DH-PLL) which includes the open-loop structure into the conventional PLL synthesizer has been studied to overcome this demerit. It operates in high speed, but the hardware complexity and power consumption are the serious problem because the DLT(digital look-up table) is usually implemented by the ROM which contains the transfer characteristic of VCO(voltage controlled oscillator). This paper proposes a new DH-PLL using a very simple DLT-replacement digital logic instead of the complex ROM-type DLT. Also, a timing synchronization circuit for the very small over-shoot and shorter settling time is designed for the ultra fast switching speed at every frequency synthesis. The hardware complexity gets decreased to about $28\%,$ as compared with the conventional DH-PLL. The high speed switching characteristic of the frequency synthesis process can be verified by the computer simulation and the circuit implementation.

• Journal of electromagnetic engineering and science
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• v.10 no.4
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• pp.219-223
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• 2010

Based on a provided closed-form wireless power transmission (WPT) efficiency formula, which may be used for any value of load, we have analyzed the WPT efficiencies between two metamaterial-inspired loop antennas in various aspects. Due to the modeling based on low frequency circuit theory, the provided formula at the center resonant frequency has been found to be accurate until when the distance between the two loop antennas increases to 15 cm (about $\lambda_0/6$ at 300 MHz). When the two loops get closer, the resonant frequency has been found to split into two in theory, simulations, and measurements. The EM-simulated and measured efficiencies at new resonant frequencies are 60.9 % and 46.3 %, respectively, at d=15 cm. With two extra rings around the loops, the maximum efficiency is enhanced to 93.7 % at d=15 cm. The effect of the additional two rings is about 30 %.

• ETRI Journal
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• v.30 no.5
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• pp.729-734
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• 2008

Wireless communication systems, such as WLAN or Bluetooth receivers, employ preamble data to estimate the channel characteristics, introducing stringent settling-time constraints. This makes the use of traditional closed-loop feedback automatic gain control (AGC) circuits impractical for these applications. In this paper, a compact feedforward AGC circuit is proposed to obtain a fast-settling response. The AGC has been implemented in a 0.35 ${\mu}m$ standard CMOS technology. Supplied at 1.8 V, it operates with a power consumption of 1.6 mW at frequencies as high as 100 MHz, while its gain ranges from 0 dB to 21 dB in 3 dB steps through a digital word. The settling time of the circuit is below 0.25 ${\mu}s$.