• Title/Summary/Keyword: Clock-Counter

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Design of Phase Locked Loop (PLL) based Time to Digital Converter for LiDAR System with Measurement of Absolute Time Difference (LiDAR 시스템용 절대시간 측정을 위한 위상고정루프 기반 시간 디지털 변환기 설계)

  • Yoo, Sang-Sun
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.25 no.5
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    • pp.677-684
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    • 2021
  • This paper presents a time-to-digital converter for measuring absolute time differences. The time-to-digital converter was designed and fabricated in 0.18-um CMOS technology and it can be applied to Light Detection and Ranging system which requires long time-cover range and 50ps time resolution. Since designed time-to-digital converter adopted the reference clock of 625MHz generated by phase locked loop, it could have absolute time resolution of 50ps after automatic calibration and its cover range was over than 800ns. The time-to-digital converter adopted a counter and chain delay lines for time measurement. The counter is used for coarse time measurement and chain delay lines are used for fine time measurement. From many times experiments, fabricated time-to-digital converter has 50 ps time resolution with maximum INL of 0.8 LSB and its power consumption is about 70 mW.

A Low Power 16-Bit RISC Microprocessor Using ECRL Circuits

  • Shin, Young-Joon;Lee, Chan-Ho;Moon, Yong
    • ETRI Journal
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    • v.26 no.6
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    • pp.513-519
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    • 2004
  • This paper presents a low power 16-bit adiabatic reduced instruction set computer (RISC) microprocessor with efficient charge recovery logic (ECRL) registers. The processor consists of registers, a control block, a register file, a program counter, and an arithmetic and logical unit (ALU). Adiabatic circuits based on ECRL are designed using a $0.35{\mu}m$ CMOS technology. An adiabatic latch based on ECRL is proposed for signal interfaces for the first time, and an efficient four-phase supply clock generator is designed to provide power for the adiabatic processor. A static CMOS processor with the same architecture is designed to compare the energy consumption of adiabatic and non-adiabatic microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is about 1/3 compared to that of the static CMOS microprocessor.

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A Fully Differential RC Calibrator for Accurate Cut-off Frequency of a Programmable Channel Selection Filter

  • Nam, Ilku;Choi, Chihoon;Lee, Ockgoo;Moon, Hyunwon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.5
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    • pp.682-686
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    • 2016
  • A fully differential RC calibrator for accurate cut-off frequency of a programmable channel selection filter is proposed. The proposed RC calibrator consists of an RC timer, clock generator, synchronous counter, digital comparator, and control block. To verify the proposed RC calibrator, a six-order Chebyshev programmable low-pass filter with adjustable 3 dB cut-off frequency, which is controlled by the proposed RC calibrator, was implemented in a $0.18-{\mu}m$ CMOS technology. The channel selection filter with the proposed RC calibrator draws 1.8 mA from a 1.8 V supply voltage and the measured 3 dB cut-off frequencies of the channel selection LPF is controlled accurately by the RC calibrator.

A Design of Low Power, High Resolution Extended-Counting A/D Converter with Small Chip Area (적은 면적을 갖는 저전력, 고해상도 확장 개수 A/D 변환기 설계)

  • 김정열;임신일
    • Proceedings of the IEEK Conference
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    • 2002.06e
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    • pp.47-50
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    • 2002
  • An extended-counting analog to digital converter (ADC) is designed to have a high resolution(14bit) with low power consumption and small dia area. First order sigma-delta modulator with a simple counter for incremental operation eliminates the need of big decimation filter in conventional sigma-delta type ADC. To improve the accuracy and linearity, extended mode of successive approximation is followed. For 14-bit conversion operation, total 263 clocks(1 clock for reset, 256 clocks for incremental operation and extended 6 clocks for successive approximation operation) are needed with the sampling rate of 10 Ms/s This ADC is implemented in a 0.6um standard CMOS technology with a die area of 1 mm ${\times}$ 0.75 mm.

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A Study on Voltammetry System Design for Realizing High Sensitivity Nano-Labeled Sensor of Detecting Heavy Metals (중금속 검출용 고감도 나노표지센서 구현을 위한 볼타메트리 시스템 설계 연구)

  • Kim, Ju-Myoung;Rhee, Chang-Kyu
    • Journal of Powder Materials
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    • v.19 no.4
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    • pp.297-303
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    • 2012
  • In this study, voltammetry system for realizing high sensitivity nano-labeled sensor of detecting heavy metals was designed, and optimal system operating conditions were determined. High precision digital to analog converter (DAC) circuit was designed to control applied unit voltage at working electrode and analog to digital converter (ADC) circuit was designed to measure the current range of $0.1{\sim}1000{\mu}A$ at counter electrode. Main control unit (MCU) circuit for controlling voltammetry system with 150 MHz clock speed, main memory circuit for the mathematical operation processing of the measured current value and independent power circuit for analog/digital circuit parts to reduce various noise were designed. From result of voltammetry system operation, oxidation current peaks which are proportional to the concentrations of Zn, Cd and Pb ions were found at each oxidation potential with high precision.

A Study on the Construction of LDV System for a Measurement of the Fluid Velocity (유체속도 측정을 위한 레이저 도플러 유속계의 구성에 관한 연구)

  • 최종원;조재흥;정명세
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.28A no.5
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    • pp.361-369
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    • 1991
  • The optics and the signal processor of dual beam laser Doppler velocimeter(LDV) was fabricated. By using the dual beam and the forward scattering, the optics part of LDV was fabricated. And the signal processor of LDV was designed by the frequency counter type using new 11:6 period timing device in order to remove error signals, and was made of the reference clock of a 500 MHz ECL oscillator. Doppler frequencies from 10KHz to 70MHz can be measured using the signal processor. In the accuracy of the period counting part, from 1.81x10**-4% to 1.27% is estimated, and in the accuracy of the validation logic part, from 0.78% to 14.78% is estimated.

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A study on the computer-controlled measuring device of complex dielectric constant (복소유전률 측정장치의 연구개발 - 컴퓨터제어 복소유전률 측정장치 -)

  • Nam, J.R.;Eum, S.O.;Kang, D.H.
    • Proceedings of the KIEE Conference
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    • 1993.07b
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    • pp.1206-1208
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    • 1993
  • This paper is to study and realize a measuring device for complex dielectric constants. The device is consisted in order of interface unit, external RAM, programmable counter, D/A converter, measuring circuit, Sample & Hold circuit, A/D converter and related control circuits. Various excitation waves are digitalized and sent to the 4096 static RAM by personal computer. These data saved in the RAM are converted to analog excitation waves through D/A converter. The frequency of excitation wave is depend on the read-out speed of the RAM according to clock pulses. Such generated waves are applied to dielectrics under test and their responses are sampled and converted to digital data through A/D converter. The computer takes the digital data and calculates finally the complex dielectric constants. The frequencies for Measurement ranges from 0.04 Hz to 10 kHz.

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Development of Chip-based Precision Motion Controller

  • Cho, Jung-Uk;Jeon, Jae-Wook
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.1022-1027
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    • 2003
  • The Motion controllers provide the sophisticated performance and enhanced capabilities we can see in the movements of robotic systems. Several types of motion controllers are available, some based on the kind of overall control system in use. PLC (Programmable Logic Controller)-based motion controllers still predominate. The many peoples use MCU (Micro Controller Unit)-based board level motion controllers and will continue to in the near-term future. These motion controllers control a variety motor system like robotic systems. Generally, They consist of large and complex circuits. PLC-based motion controller consists of high performance PLC, development tool, and application specific software. It can be cause to generate several problems that are large size and space, much cabling, and additional high coasts. MCU-based motion controller consists of memories like ROM and RAM, I/O interface ports, and decoder in order to operate MCU. Additionally, it needs DPRAM to communicate with host PC, counter to get position information of motor by using encoder signal, additional circuits to control servo, and application specific software to generate a various velocity profiles. It can be causes to generate several problems that are overall system complexity, large size and space, much cabling, large power consumption and additional high costs. Also, it needs much times to calculate velocity profile because of generating by software method and don't generate various velocity profiles like arbitrary velocity profile. Therefore, It is hard to generate expected various velocity profiles. And further, to embed real-time OS (Operating System) is considered for more reliable motion control. In this paper, the structure of chip-based precision motion controller is proposed to solve above-mentioned problems of control systems. This proposed motion controller is designed with a FPGA (Field Programmable Gate Arrays) by using the VHDL (Very high speed integrated circuit Hardware Description Language) and Handel-C that is program language for deign hardware. This motion controller consists of Velocity Profile Generator (VPG) part to generate expected various velocity profiles, PCI Interface part to communicate with host PC, Feedback Counter part to get position information by using encoder signal, Clock Generator to generate expected various clock signal, Controller part to control position of motor with generated velocity profile and position information, and Data Converter part to convert and transmit compatible data to D/A converter.

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Design of Low Voltage 1.8V, Wide Range 50∼500MHz Delay Locked Loop for DDR SDRAM (DDR SDRAM을 위한 저전압 1.8V 광대역 50∼500MHz Delay Locked Loop의 설계)

  • Koo, In-Jae;Chung, Kang-Min
    • The KIPS Transactions:PartA
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    • v.10A no.3
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    • pp.247-254
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    • 2003
  • This paper describes a Delay Locked Loop (DLL) with low supply voltage and wide lock range for Synchronous DRAM which employs Double Data Rate (DDR) technique for faster data transmission. To obtain high resolution and fast lock-on time, a new type of phase detector is designed. The new counter and lock indicator structure are suggested based on the Dual-clock dual-data Flip Flop (DCDD FF). The DCDD FF reduces the size of counter and lock indicator by about 70%. The delay line is composed of coarse and fine units. By the use of fast phase detector, the coarse delay line can detect minute phase difference of 0.2 nsec and below. Aided further by the new type of 3-step vernier fine delay line, this DLL circuit achieves unprecedented timing resolution of 25psec. This DLL spans wide locking range from 500MHz to 500MHz and generates high-speed clocks with fast lock-on time of less than 5 clocks. When designed using 0.25 um CMOS technology with 1.8V supply voltage, the circuit consumes 32mA at 500MHz locked condition. This circuit can be also used for other applications as well, such as synchronization of high frequency communication systems.

Dual Mode Buck Converter Capable of Changing Modes (모드 전환 제어 가능한 듀얼 모드 벅 변환기)

  • Jo, Yong-min;Lee, Tae-Heon;Kim, Jong-Goo;Yoon, Kwang Sub
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.10
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    • pp.40-47
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    • 2016
  • In this paper, a dual mode buck converter with an ability to change mode is proposed, which is suitable particularly for portable device. The problem of conventional mode control circuit is affected by load variation condition such as suddenly or slowly. To resolve this problem, the mode control was designed with slow clock method. Also, when change from the PFM(Pulse Frequency Modulation) mode to the PWM(Pulse Width Modulation) mode, to use the counter to detect a high load. And the user can select mode transition point in load range from 20mA to 90mA by 3 bit digital signal. The circuits are implemented by using BCDMOS 0.18um 2-polt 3-metal process. Measurement environment are input voltage 3.7V, output voltage 1.2V and load current range from 10uA to 500mA. And measurement result show that the peak efficiency is 86% and ripple voltage is less 32mV.