• Journal of Korea Society of Industrial Information Systems
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• v.20 no.1
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• pp.1-7
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• 2015

In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration has been proposed for digital controlled DC-DC converters. The hybrid structure of DPWM combines a 6-bit differential tapped delay line ring-mux digital-to-time converter (DTC) schema and a 6-bit counter-comparator DTC schema, resulting in a power and area saving solution. Furthermore, since the 6-bit differential delay line ring oscillator serves as the clock to the high 6-bit counter-comparator DTC, a high frequency clock is eliminated, and the power is significantly saved. In order to have a simple delay cell and flexible delay time controllability, a voltage controlled inverter is adopted to build the deferential delay cell, which allows fine-tuning of the delay time. The PT calibration circuit is composed of process and temperature monitors, two 2-bit flash ADCs and a lookup table. The monitor circuits sense the PT (Process and Temperature) variations, and the flash ADC converts the data into a digital code. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.7
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• pp.816-821
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• 2019

A counter-type time-to-digital converter was designed using a dual edge T flip-flop. The time-to-digital converter was designed with a $0.18{\mu}m$ CMOS process at a supply voltage of 1.5 volts. In a typical time-to-digital converter, when the period of the clock is T, a conversion error corresponding to the period of the clock occurs due to the asynchronism between the input signal and the clock. However, the clock of the time-to-digital converter proposed in this paper is generated in synchronization with the start signal which is the input signal. As a result, conversion errors that may occur due to asynchronization of the start signal and the clock do not occur. The flip-flops constituting the counters are composed of dual-edge flip-flops operating at the positive and negative edges of the clock to improve the resolution.

• ETRI Journal
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• v.28 no.1
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• pp.31-44
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• 2006

In a packet switching network, congestion is unavoidable and affects the quality of real-time traffic with such problems as delay and packet loss. Packet fair queuing (PFQ) algorithms are well-known solutions for quality-of-service (QoS) guarantee by packet scheduling. Our approach is different from previous algorithms in that it uses hardware time achieved by sampling a counter triggered by a periodic clock signal. This clock signal can be provided to all the modules of a routing system to get synchronization. In this architecture, a variant of the PFQ algorithm, called digitized delay queuing (DDQ), can be distributed on many line interface modules. We derive the delay bounds in a single processor system and in a distributed architecture. The definition of traffic contribution improves the simplicity of the mathematical models. The effect of different time between modules in a distributed architecture is the key idea for understanding the delay behavior of a routing system. The number of bins required for the DDQ algorithm is also derived to make the system configuration clear. The analytical models developed in this paper form the basis of improvement and application to a combined input and output queuing (CIOQ) router architecture for a higher speed QoS network.

• Journal of Ocean Engineering and Technology
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• v.11 no.4
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• pp.239-248
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• 1997

The nesting of parts cut on raw steel plate has been a subject of interest to the shipbuilding industry for many years. "Nesting" is defined operation of layout of the parts on the raw material with minimizing the waste rate. Therefore, it is very important to optimize the cutting area. Since the existing nesting programs are prepared for expensive workstations and the expert, it is needed to develop nesting program for personal computer to improve the technology of small/middle sized shipyards and their productivity. This study involves development and application of appropriate optimization technique to solve the problem of plate nesting. And the appropriate D/B for storing nesting data developed, the function of D/B is introduced in this paper.his paper.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.152-156
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• 2013

This paper presents a fast-lock dual-loop successive approximation register-controlled duty-cycle corrector (SARDCC) circuit using a mixed (binary+sequential) search algorithm. A wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy have been achieved by utilizing the dual-loop architecture and the binary search SAR that achieves the fast duty-cycle correcting property. By transforming the binary search SAR into a sequential search counter after the first DCC lock-in, the proposed dual-loop SARDCC keeps the closed-loop characteristic and tracks variations in process, voltage, and temperature (PVT). The measured duty cycle error is less than ${\pm}0.86%$ for a wide input duty-cycle range of 15-85 % over a wide frequency range of 0.5-2.0 GHz. The proposed dual-loop SARDCC is fabricated in a 0.18-${\mu}m$, 1.8-V CMOS process and occupies an active area of $0.075mm^2$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.522-523
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• 2017

Analog-to-Digital converter is designed using a current conveyor circuit and a time-to-digital converter. The analog voltage is sampled using the current conveyor circuit and then the voltage is converted to time information by the discharge of the sampling voltage. The time information is converted to digital value by the counter-type time-to-digital converter. In order to reduce the converted error the clock is synchronized with the time information pulse.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.5
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• pp.787-795
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• 1994

In this paper, we have proposed a bit synchronization algorithm which extracts the synchronized clock for random NRZ signal and designed a circuit followed by its performance analysis. The synchronization circuit consists of the Data Transition Detector and Mod 64 Counter, Phase Comparison and Controller, 64 Divider. The data input rate and master clock rate are 16 Kbps and 4.096MHz, respectively. The phase is compensated by 1/64 of the data signal period for every data bit. Through a series of experiments, the maximum immunity of phase jiter for input signal and the deviation of the recovered clock are measured 23.8% and 1.6%, respectively. The fully digital synchronization circuit is simple to implement into signal IC chip and also effective for the low speed digital mobile communications.

• Journal of Advanced Navigation Technology
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• v.18 no.5
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• pp.429-436
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• 2014

This paper proposes three methods of the time synchronization for Pseudolite and GPS and analyzes pseudolite time synchronization error factors for software based performance evaluation on proposed time synchronization methods. Proposed three time synchronization methods are pseudolite time synchronization station construction method, method by using UTC(KRIS) clock source and GPS timing receiver based time synchronization method. Also, we analyze pseudolite time synchronization error factors such as errors of pseudolite clock and reference clock, time delay as clock transmission line, measurement error of time interval counter and error as clock synchronization algorithm to design simulation platform for performance evaluation of pseudolite time synchronization.

• Journal of the Korea Society of Computer and Information
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• v.4 no.1
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• pp.28-37
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• 1999

In this paper. we developed a delay test architecture and test procedure for clocked 5-bit asynchronous counter circuit based on boundary scan architecture. To develope, we analyze the problems of conventional method on delay test for clocked sequential circuit in boundary scan architecture. This paper discusses several problems of delay test on boundary scan architecture for clocked sequential circuit. Conventional test method has some problems of improper capture timing, of same pattern insertion, of increase of test time. We suggest a delay test architecture and test procedure, is based on a clock count-generation technique to generate continuous clocks for clocked input of CUT. The simulation results or 5-bit counter shows the accurate operation and effectiveness of the proposed delay test architecture and procedure.

• Proceedings of the Optical Society of Korea Conference
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• 2001.02a
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• pp.74-75
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• 2001

현재의 통신망에서는 clock recovery, regeneration 등을 전기적으로 처리하고 있으나 처리속도의 한계가 있고, 미래의 초고속 네트웍은 이러한 전기적 신호처리의 속도한계를 극복하는 기술이 필요하다. 그러므로, 고속의 광교환과 광신호처리 등 광신호를 전기적으로 바꾸거나 제어하지 않고 전광으로 처리하는 기술에 대한 연구가 진행되고 있으며 이러한 전광신호 처리에 고속의 전광 논리소자가 요구된다. 초기의 전광 논리소자 연구에서는 AND, OR, NOR, XOR 등의 기본 논리 기능이 주로 구현되었으며 이를 활용하여 Shift Register, Binary counter, 전광 반가산기, 직/병렬 데이터 변환기와 같은 복합기능 논리소자의 구현 연구가 이루어지고 있다. (중략)