• Journal of Electrical Engineering and Technology
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• v.7 no.4
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• pp.626-635
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• 2012

Most of single frequency GPS receivers utilize low-quality crystal oscillators. If a lowquality crystal oscillator is utilized as the time reference of a GPS receiver, the receiver's clock bias grows very fast due to its inherent low precision and poor stability. To prevent the clock bias becoming too large, large clock jumps are intentionally injected to the clock bias and the time offset for clock steering purpose. The abrupt changes in the clock bias and the time offset, if not properly considered, induce serious accuracy degradation in relative differential positioning. To prevent the accuracy degradation, this paper proposes an efficient and systematic method to eliminate the undesirable clock jump effects. Experiment results based on real measurements verify the effectiveness of the propose method.

• ETRI Journal
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• v.35 no.1
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• pp.158-161
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• 2013

This letter proposes a low-power current-steering digital-to-analog converter (DAC). The proposed DAC reduces the clock power by cutting the clock signal to the current-source cells in which the data will not be changed. The 10-bit DAC is implemented using a $0.13-{\mu}m$ CMOS process with $V_{DD}$=1.2 V. Its area is $0.21\;mm^2$. It consumes 4.46 mW at a 1-MHz signal frequency and 200-MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25-MHz and 10-MHz signal frequencies, respectively. The measured spurious free dynamic ranges are 72.8 dB and 56.1 dB at 1-MHz and 50-MHz signal frequencies, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.39-45
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• 2011

This paper proposes a low power current-steering 10-bit DAC selecting clock enable signal. The proposed DAC reduces the clock power by cutting the clock signal to the current-source cells in wihich the data will not be changed. The proposed DAC was implemented using a 0.13${\mu}m$ CMOS process with $V_{DD}=1.2V$. Its core area is 0.21$mm^2$. It consumes 4.46mW at 1MHz signal frequency and 200MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25MHz and 10MHz signal frequencies, respectively. The measured SFDRs are 72.8dB and 56.1dB at 1MHz and 50MHz signal frequencies, respectively.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.465-466
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• 2006

In this paper, novel analog duty cycle corrector (DCC) with a digital duty error detector is proposed. The digital duty error detector measures the duty error of the clock and converts it into a digital code. This digital code is then used to accurately correct the duty ratio by adaptively steering the charge-pump current. The proposed duty cycle corrector was implemented using an 80nm DRAM process with 1.8V supply voltage. The simulation result shows that the proposed duty cycle corrector improves the settling time up to $70{\sim}80%$ at 500MHz clock frequency for the same duty correction accuracy as the conventional analog DCC.

• Journal of Auto-vehicle Safety Association
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• v.13 no.3
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• pp.20-25
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• 2021

Flexural resistance evaluation of FFC (Flexible Flat Cable) was performed according to the grain size of rolled copper foil by adding 0.1wt% silver (Ag) and electrodeposited copper foil by slitting method after heat-treatment. These methods are aimed at enhancing the flexural durability of the FFC by growing the grain size of copper foil. By increasing the grain size of the copper foil and minimizing the miss-orientation at grain boundaries, the residual stress at the grain boundaries of the copper foil is reduced and the durability of the FFC is improved. Maximizing an average grain size of copper foil can be got a good solution in order to enhance the durability of the FFC or FPCB (Flexible Printed Circuit Board).

• Journal of the Korea Academia-Industrial cooperation Society
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• v.22 no.1
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• pp.402-408
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• 2021

Vehicle engineering analysis in the event of an accident caused by a car built on mechanical design has not been investigated in-depth but relies on the subjective experience knowledge of the investigator. This study analyzed the correlation between the speed, progress, steering, and braking before impact, which is consistent with the final stop position, by drawing a site situation chart using the CAD (CAD) program and repeating 250 crashes using the PC-Crash program. The following situations were investigated: lower impact velocity; greater impact speed of the vehicle, which is not affected significantly by the departure angle; higher vehicle speed, such as the effective impact velocity, after the impact; higher vehicle speed; and lower vehicle speed. (Ed note: I am unsure what you are saying here. It appears contradictory and not a complete sentence. Please check the changes.)The simulation results of this study identified the process of returning to the magnetic progression lane after recognizing the opposite porter while Mighty was carried out on the uphill left-curve section in a position that crossed the center line, and the collision of the porter's front left side, pushing the porter in the right diagonal direction and making the front stop towards approximately 11 o'clock.

• Journal of Advanced Navigation Technology
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• v.20 no.1
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• pp.8-14
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• 2016

High-level conceptual design analysis results of satellite communication system for Korea augmentation satellite system (KASS) satellite communication system, which is a part of KASS and consisted of KASS uplink Stations and two leased GEO is presented in this paper. We present major functions such as receiving correction and integrity message from central processing system, taking forward error correction for the message, modulating and up converting signal and conceptual design analysis for concepts for design process, GEO precise orbit determination for GEO ranging that is additional function, and clock steering for synchronization of clocks between GEO and GPS satellites. In addition to these, KASS requires 2.2 MHz for SBAS Augmentation service and 18.5 MHz for Geo-ranging service as minimum bandwidths as a results of service performance analysis of GEO ranging with respect to navigation payload(transponder) RF bandwidth is presented. These analysis results will be fed into KASS communication system design by carrying out final analysis after determining two GEOs and sites of KASS uplink stations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.1-9
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• 2009

In this paper, a small area 12-bit 300MSPS CMOS Digital-to-Analog Converter(DAC) is proposed for display systems. The architecture of the DAC is based on a current steering 6+6 segmented type, which reduces non-linearity error and other secondary effects. In order to improve the linearity and glitch noise, an analog current cell using monitoring bias circuit is designed. For the purpose of reducing chip area and power dissipation, furthermore, a noble self-clocked switching logic is proposed. To verify the performance, it is fabricated with $0.13{\mu}m$ thick-gate 1-poly 6-metal N-well Samsung CMOS technology. The effective chip area is $0.26mm^2$ ($510{\mu}m{\times}510{\mu}m$) with 100mW power consumption. The measured INL (Integrated Non Linearity) and DNL (Differential Non Linearity) are within ${\pm}3LSB$ and ${\pm}1LSB$, respectively. The measured SFDR is about 70dB, when the input frequency is 15MHz at 300MHz clock frequency.