• Proceedings of the IEEK Conference
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• 2000.06e
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• pp.183-186
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• 2000

In this paper we propose a new architecture of a programmable digital automatic gain controller(AGC) for analog interface in mixed mode systems. Compared with conventional analog AGCs which have difficulties in integration due to large capacitors, the proposed AGC is easily integrated. So the production cost can be reduced. In addition, The proposed AGC has a better performance in temperature, and power supply variations, and substrate noise than analog counterparts do. To prevent erroneous operations of the AGC due to noise, a mal-function preventer is newly proposed. In addition, to achieve an optimized AGC time constant, we propose a logic block which controls an up-down counting clock. This is directly related to the changing speed of the AGC gain. Implemented with a 0.25 $\mu\textrm{m}$ 1-poly, 5-metal CMOS parameters, the AGC operates from a single 2.5V power supply with the dynamic range of 36.ldB and occupies active area of 500$\mu\textrm{m}$${\times}$600$\mu\textrm{m}$

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.2
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• pp.102-106
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• 2003

This paper describes novel low-power high-speed flip-flop called dual edge-triggered NAND keeper flip-flop (DETNKFF). The flip-flop achieves substantial power reduction by incorporating dual edge-triggered operation and by eliminating redundant transitions. It also minimizes the data-to-output latency by reducing the height of transistor stack on the critical path. Moreover, DETNKFF allows negative setup time to provide useful attribute of soft clock edge by incorporating the pulse-triggered operation. The proposed flip-flop was designed using a $0.35{\;}\mutextrm{m}$ CMOS technology. The simulation results indicate that, for the typical input switching activity of 0.3, DETNKFF reduces power consumption by as much as 21 %. Latency is also improved by about 6 % as compared to the conventional flip-flop. The improvement of power-delay product is also as much as 25 %.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.117-123
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• 2016

In general, PCM (Phase Change Memory) is unsuitable as a main memory because it has limitations: high read/write latency and low endurance. However, the DRAM&PCM hybrid memory with the same level is one of the effective structures for a next generation main memory because it can utilize an advantage of both DRAM and PCM. Therefore, it needs an effective page management method for exploiting each memory characteristics dynamically and adaptively. So we aim reducing an access time and write count of PCM by using an effective page replacement. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the PCM access count by around 60% and the PCM write count by 42% given the same PCM size, compared with Clock-DWF algorithm.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.7
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• pp.1026-1030
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• 2015

In this paper, we propose a signal processing board of an optical delay simulator for evaluating a long-range laser range finder and a laser target designator. We improved the accuracy by applying the clock multiplication and the correction of error gradient. To evaluate the performance of the proposed method, we implemented a prototype board and performed experiments. As a result, we implemented the optical delay simulator with resolution less than 0.7m in measuring distance 60km and a standard deviation of 0.041m. The PRF code detection logic and generation logic have a stability less than 0.03% and 0.08% compared to the NATO standard, respectively.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.12
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• pp.1675-1682
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• 2014

In this paper, we propose a precise time management and time synchronization based on real-time data storage and transmission scheme in design of seismic data acquisition system for urban earthquake disaster preventing system (UEDPS). It is possible to improve the performance of the existing research results through the proposed methods. To evaluate the performances of the proposed methods, we implemented a prototype system(H/W & S/W) and performed some experiments with real seismic data and test equipment generated data as the input.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.337-340
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• 2009

In general, channel information of received DTV signal analyzed based on symbol timing clock with only In-phase information in DTV receiver. This paper presents technical requirements of channel analysis system for DTV reception signal. In order to meet such requirements and measure more accurate magnitude and phase of channel information, compensation method for the quadrature information from measured in-phase data is proposed. The proposed channel analysis system is implemented with a commercial DTV chipset and provides fast data analysis with good connectivity with field test vehicles. Computer simulation and laboratory test results are provided to figure out the performance of the proposed channel analysis system for DTV signal.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4A
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• pp.301-309
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• 2002

In this paper, we propose the effective implementation of various nonlinear combiners using by PS-LFSR: m-parallel memoryless-nonlinear combiner, m-parallel memory-nonlinear combiner, m-parallel nonlinear filter function, and m-parallel clock-controlled function. Finally, we propose m-parallel LILI-128 stream cipher as an example of the parallel implementation, and we determine its cryptographic security and performance.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.9
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• pp.1652-1659
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• 2008

With the increase of huge amount of data in network systems, ultimate high-speed network has become an essential requirement. In such systems, the encryption and decryption process for security becomes a bottle-neck. For this reason, the need of hardware implementation is strongly emphasized. In this study, a mixed inner and outer round pipelining architecture is introduced to achieve high speed performance of ARIA hardware. Multiplexers are used to control the lengths of rounds for 3 types of keys. Merging of encryption module and key initialization module increases the area efficiency. The proposed hardware architecture is implemented on reconfigurable hardware, Xilinx Virtex2-pro. The hardware architecture in this study shows that the area occupied 6437 slices and 128 BRAMs, and it is translated to throughput of 24.6Gbit/s with a maximum clock frequency of 192.9MHz.

• Journal of Biomedical Engineering Research
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• v.6 no.2
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• pp.15-22
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• 1985

We have developed a microprogramir!able signal processor for real-time ultrasonic signal processing. Processing speed was increased by the parallelism in horizontal microprogram using 104bits microcode and the Pipelined architecture. Control unit of the signal processor was designed by microprogrammed architec- ture and writable control store (WCS) which was interfaced with host computer, APPLE- ll . This enables the processor to develop and simulate various digital signal processing algorithms. The performance of the processor was evaluated by the Fast Fourier Transform (FFT) program. The execution time to perform 16 bit 1024 points complex FF7, radix-2 DIT algorithm, was about 175 msec with IMHz master Clock. We can use this processor to Bevelop more efficient signal processing algorithms on the biological signal processing.

• Proceedings of The Korean Society of Agricultural and Forest Meteorology Conference
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• 2003.09a
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• pp.39-41
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• 2003

The crop growth simulation model could be adopted to evaluate the impact not only of the long term climate change such as atmosphere $CO_2$ concentration rising and global warming but also of the predicted short term weather variability on the national crop production. There are several growth simulation models for predicting rice crop performance such as ORYZA1, CERES-Rice, Rice Clock Model, and SIMRIW.(omitted)