• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.6
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• pp.1133-1138
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• 2007

DLLs(Delay Locked Loops) have widely been used in many systems in order to achieve the clock synchronization. A SMD (Synchronous Mirror Delay) structure is used both for skew reduction and for DCC (Duty Cycle Correction). In this paper, a SMD based DLL with DCC using Reduced Delay Lines is proposed in order to reduce the clock skew and correct the duty cycle. The merged structure allows the forward delay array to be shared between the DLL and the DCC, and yields a 25% saving in the number of the required delay cells. The designed chip was fabricated using a $0.25{\mu}m$ 1-poly, 4-metal CMOS process. Measurement results showed the 3% duty cycle error when the input signal ranges from 80% to 20% and the clock frequency ranges from 400MHz to 600MHz. The locking operation needs 3 clock and duty correction requires only 5 clock cycles as feature with SMD structure.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.677-680
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• 2003

In this paper, the analysis of practical end-to-end delay in worst case is performed for distributed control system considering the implementation of the system. The control system delay is composed of the delay caused by multi-task scheduling of operating system, the delay caused by network communication, and the delay caused by the asynchronous between them. Through simulation tests based on CAN(Controller Area Network), the proposed end-to-end delay in worst case is validated. Additionally, online clock synchronization algorithm is proposed here for the control system. Through another simulation test, the online algorithm is proved to have better performance than offline one in the view of network bandwidth utilization.

• 한국정보통신설비학회:학술대회논문집
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• 2005.08a
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• pp.159-165
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• 2005

The proposed optical transmitter is composed of FF(flip flop) , PLL (phase locked loop), reference clock generator, serializer and LD driver 10x250 Mb/s data arrays are translated to the 2.5 Gb/s data signal by serializer. In this case, 1 data bus is allocated usually as a reference clock for synchronization. In this proposed optical transmitter, 125 MHz reference clock is generated from 10x250 Mb/s data arrays by reference clock generator. From this method. absent of reference clock bus is available and more data transmission become possible. To achieve high speed operation, the serializer circuit is designed as two stacks. For 10:1 serialization, 10 clocks that have 1/10 lambda differences is essential, so the VCO (voltage controlled oscillator) composed of 10 delay buffers is designed. PLL is for runing at 250 MHz, and dual PFD(phase frequency detector) is adopted for fast locking time. The optical transmitter is designed by using 0.35 um CMOS technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37C no.10
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• pp.894-900
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• 2012

Indoor wireless positioning system uses ranging information of beacons in order to precisely estimate a tag location. To estimate distance between each beacons and tag, the system calculates arrival time of a tag pulse with clock of each beacon including independent clock offset. This clock offset seriously affects the performance of ranging and positioning. We propose in this paper a clock offset compensation method to solve this problem. To verify the performance of the proposed method, we simulated location estimation with random clock offset between -1,000ppm and 1,000ppm, and the result shows that the proposed scheme effectively solves the clock offset problem.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.980-986
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• 2002

In the fast data communication system, synchronized by a clock source, the loss of data will often occur due to several reasons as a differential routing path between data and clock, a differential propagation delay of components or an unstable phase of clock and data by external noise. In this paper, we describe the ASIC implementation of the data compensation circuit which can detect the data loss from above problems and recovery to original data with stable synchronization. Especially it supports a strong stability and a good BER in the communication system for fast data transfer as optic area. This circuit is implemented by Verilog HDL and available to the digital ASIC implementations related to fast data transfer.

• 한국정보통신설비학회:학술대회논문집
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• 2009.08a
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• pp.275-280
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• 2009

Femtocells are viewed as a promising option for mobile operators to improve coverage and provide high-data-rate services in a cost-effective manner Femtocells can be used to serve indoor users, resulting in a powerful solution for ubiquitous indoor and outdoor coverage. TThe frequency accuracy and phase alignment is necessary for ensuring the quality of service (QoS) forapplications such as voice, real-time video, wireless hand-off, and data over a converged access medium at the femtocell. But, the GPS has some problem to be used at the femtocell, because it is difficult to set-up, depends on the satellite condition, and very expensive. The IEEE 1588 specification provides a low-cost means for clock synchronisation over a broadband Internet connection. The Time of Packet (ToP) specified in IEEE 1588 is able to synchronize distributed clocks with an accuracy of less than one microsecond in packet networks. However, the timing synchronization over packet switched networks is a difficult task because packet networks introduce large and highly variable packet delays. This paper proposes an enhanced filter algorithm to reduce ths packet delay variation effects and maintain ToP slave clock synchronization performance. The results are presented to demonstrate in the intra-networks and show the improved performance case when the efficient ToP filter algorithm is applied.

• Aerospace Engineering and Technology
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• v.3 no.1
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• pp.109-116
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• 2004

In a satellite time management system, the GPS-based clock synchronization technique[1] has the merits of precision time management by knowing the time difference or the error between the OBT(On Board Time) of the internal processors and GPS time every second. It can be realized employing the DPLL(Digital Phase Loop Lock) and FEP(Front End Processor) circuitry for the clock synchronization[2]. In this paper, a refined DPLL & FEP scheme is proposed to provide the precision, stability and robustness of the operation, which is to compensate the errors and noise of the GPS signal, and also to cope with the case when the GPS signal is lost due to several reasons. The simulation and HIL (Hardware In the Loop) test results using the FM(Flight Model) in the course of KOMPSAT-2(Korea Multi Purpose Satellite-2) design and development are illustrated to demonstrate the salient features of this methodology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.12A
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• pp.971-981
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• 2009

The coordination of distributed entities and events requires time synchronization. Precision time synchronization enables a variety of extensions of applications and provides much accurate information. The IEEE 1588 precision time protocol (PTP) provides a standard method to synchronize devices in a network. This paper deals with the design and implementation of a PTP gateway to extend IEEE 1588 to Zigbee networks. The PTP gateway can not only extend IEEE 1588 to Zigbee networks but also share the same time reference using IEEE 1588 between two or more Zigbee networks. This paper also presents experiments and performance evaluation of time synchronization using the PTP gateway. Our result established a method for nodes in a network to maintain their clocks to within a 300 nanosecond offset from the reference clock of a master node via Ethernet.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.880-883
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• 2002

In this paper, we propose the synchronization recovery algorithm which is suitable to wireless multimedia of wireless channel situation which is being used OFDM signaling method. The basic of the suggested clock synchronization. restoration Algorithm is to getting the shock response of channel or getting the multipath strength profile through IFFT after the getting the frequency, response of deducted channel from channel deductor of receiver and to trace the location in the channel energy concentrated area of timing area. And it also analysis the start point of 64-QAM and 16-QAM if the sampling clock offset has the sample of $\pm$1-3, and we identified the occurance of performance deterioration when occures more than 2 samples of offset to compare with star point and BER performance in optimum sampling point result of BER performance checking, and we know that the recovery algorithm proposed algorithm also provide excellent synchronization characteries under frequency, selecting fading channel as result of simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.9
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• pp.1069-1080
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• 2016

TDOA(Time Difference Of Arrival)-based localization system such as the passive surveillance system performs the time synchronization between the receivers after separated installing multiple receivers to set the same clock for all receivers. And it estimates 2D(or 3D) location of the target by solving intersection of the multiple hyperbola(or hyperboloid) using TDOA. To perform time synchronization, one receiver must be set to the master, and it provide the reference data to compensate the clock of the rest of the slaves. The positioning accuracy of TDOA-based localization system is changed in accordance with the master that is selected among multiple receivers. So, the optimum receiver which is selected among multiple receivers must be set to master to get best performance in the considered deployment of receivers. In this paper, we propose a selection scheme of master receiver for time synchronization using DOP(Dilution Of Precision) which is based on location of the target and the multiple receivers. The proposed scheme has low complexity and short processing time, and it is easy to automate in the TDOA-based localization systems.