• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.23 no.7
• /
• pp.816-821
• /
• 2019

A counter-type time-to-digital converter was designed using a dual edge T flip-flop. The time-to-digital converter was designed with a $0.18{\mu}m$ CMOS process at a supply voltage of 1.5 volts. In a typical time-to-digital converter, when the period of the clock is T, a conversion error corresponding to the period of the clock occurs due to the asynchronism between the input signal and the clock. However, the clock of the time-to-digital converter proposed in this paper is generated in synchronization with the start signal which is the input signal. As a result, conversion errors that may occur due to asynchronization of the start signal and the clock do not occur. The flip-flops constituting the counters are composed of dual-edge flip-flops operating at the positive and negative edges of the clock to improve the resolution.

• KIPS Transactions on Computer and Communication Systems
• /
• v.3 no.9
• /
• pp.293-300
• /
• 2014

TDMA(Time Division Multiple Access) is a channel access scheme for shared medium networks. The shared frequency is divided into multiple time slots, some of which are assigned to a user for communication. Techniques for TDMA can be categorized into two classes: synchronous and asynchronous. Synchronization is not suitable for small scale networks because it is complicated and requires additional equipments. In contrast, in DESYNC, a biologically-inspired algorithm, the synchronization can be easily achieved without a global clock or other infrastructure overhead. However, DESYNC spends a great deal of time to complete synchronization and does not guarantee the maximum time to synch completion. In this paper, we propose a lightweight synchronization scheme, C-DESYNC, which counts the number of participating nodes with GP (Global Packet) signal including the information about the starting time of a period. The proposed algorithm is mush simpler than the existing synchronization TDMA techniques in terms of cost-effective method and guarantees the maximum time to synch completion. Our simulation results show that C-DESYNC guarantees the completion of the synchronization process within only 3 periods regardless of the number of nodes.

• Journal of Satellite, Information and Communications
• /
• v.10 no.1
• /
• pp.71-76
• /
• 2015

In this paper, we developed the hardware GPS signal generator for generating a satellite navigation signal synchronized with Live GPS signal signals and analyzed the performance of signal genterator thorough the experiment For a hardware implementation of the GPS navigation signal synchronous generator, the GPS module may receive a GPS signal in order to generate the same signal as the operation that is transmitted from the current GPS satellite and the synchronized time information and the GPS satellites using the Novatel Inc. OEMStar.In. For generating the GPS synchronization signal, the GPS navigation signal generator was adjusted to a reference clock using the GPS clock synchronous information provided by the GPS receiving module and GPS signals also generated in consideration of the delay of the internal hardware of the generator. In this paper, we analyzed the effect of the receiver via the signal switching between Live GPS signal and generates a signal to measure the performance of the GPS navigation synchronization signal generator. It was confirmed that by the seamless operation of the signal even the moment that the switching of the generated signal from Live GPS signal has occurred through experimentation.

• Journal of the Institute of Convergence Signal Processing
• /
• v.6 no.4
• /
• pp.206-211
• /
• 2005

We describe the design for a correlator and an access code generator in bluetooth system. These are used for a connection setting, a packet decision and a clock synchronization between Bluetooth units. The correlator consists of two blocks; carry save adder based on Wallace tree and threshold-value decision block. It determines on an useful packet and clock-synchronization for input signal of 1.0Mbps through the sliding-window correlating. The access-code generator also consists of two blocks; BCH(Bose-Chadhuri-Hocquenghem) cyclic encoder and control block. It generates the access-codes according to four steps' generation process based on Bluetooth standard. In order to solve synchronization problem, we make use of any memory as a pseudo random sequence. The proposed correlator and access-code generator were coded with VHDL. An FPGA Implementation of these modules and the simulation results are proved by Xilinx chip. The critical delay and correlative margin based on synthesis show the 4.689ns and the allowable correlation-error up to 7-bit.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.7 s.361
• /
• pp.62-70
• /
• 2007

In this paper, we design a mobile camera processor to support the MIPI CSI-2 and DPHY specification. The lane management sub-layer of CIS2 handles multi-lane configuration. Thus conceptually, the transmitter and receiver have each independent buffer on multi lanes. In the proposed architecture, the independent buffers are merged into a single common buffer. The single buffer architecture can flexibly manage data on multi lanes though the number of supported lanes are mismatched in a camera processor transmitter and a host processor. For a key issue for the data synchronization problem, the synchronization start codes are added as the starting for image data. We design synchronization logic to synchronize the received clock and to generate the byte clock. We present the verification results under proposed test bench. And we show the waves of simulation and logic synthesis results of the designed processor.

• Journal of Positioning, Navigation, and Timing
• /
• v.4 no.2
• /
• pp.67-72
• /
• 2015

Power grid techniques are distributed over general power systems ranging from power stations to power transmission, power distribution, and users. To monitor and control the elements and performance of a power system in real time in the extensive area of power generation, power transmission, wide-area monitoring (WAM) and control techniques are required (Sattinger et al. 2007). Also, to efficiently operate a power grid, integrated techniques of information and communication technology are required for the application of communication network and relevant equipment, computing, and system control software. WAM should make a precise power grid measurement of more than once per cycle by time synchronization using GPS. By collecting the measurement values of a power grid from substations located at faraway regions through remote communication, the current status of the entire power grid system can be examined. However, for GPS that is used in general national industries, unexpected dangerous situations have occurred due to its deterioration and jamming. Currently, the power grid is based on a synchronization system using GPS. Thus, interruption of the time synchronization system of the power system due to the failure or abnormal condition of GPS would have enormous effects on each field such as economy, security, and the lives of the public due to the destruction of the synchronization system of the national power grid. Developed countries have an emergency substitute system in preparation for this abnormal situation of GPS. Therefore, in Korea, a system that is used to prepare for the interruption of GPS reception should also be established on a long-term basis; but prior to this, it is required that an evaluation technique for the time synchronization performance of a GPS receiver using an atomic clock within the power grid. In this study, a monitoring system of time synchronization based on GPS at a power grid was implemented, and the results were presented.

• Journal of KIISE:Information Networking
• /
• v.34 no.5
• /
• pp.370-378
• /
• 2007

In wireless sensor networks (WSNs), thousands of sensors are often deployed in a hostile environment. In such an environment, WSNs can be applied to various applications by using the absolute or relative location information of the sensors. Until now, the time-of-arrival (TOA) based localization method has been considered most accurate. In the TOA method, however, inaccuracy in distance estimation is caused by clock drift and clock skew between sensor nodes. To solve this problem, several numbers of periodic time synchronization methods were suggested while these methods introduced overheads to the packet traffic. In this paper, we propose a new localization method based on multiple round-trip times (RTOA) of a signal which gives more accurate distance and location estimation even in the presence of clock skew between sensor nodes. Our experimental results show that the Proposed RTOA method gives up to 93% more accurate location estimation.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.33B no.3
• /
• pp.62-68
• /
• 1996

A CMOS transmitter ASIC for the ATM switching system etc., was designed to transmit 155.52 Mbps serial data transformed from 19.44 Mbps parallel data. 155.52 MHz clock for synchronization of data is genrated using reference 19.44 MHz clock by an analog PLL while parallel to serial data conversion is done by a digital circuit. Circuit simulations confirm that PLL locking and data conversion are accomplished successfully. The area of the designed ASIC chip is 1.3${\times}1.0mm^2$. The locking time and the power consumption of the chip are about 600 nsec and less than 150 mW, respectively.

• Proceedings of the Korean Information Science Society Conference
• /
• 2008.06b
• /
• pp.500-503
• /
• 2008

분산 컴포넌트 시스템에서 여러 컴포넌트가 맞물려 서비스를 수행할 때 기준이 되는 시간이 필요하고 각 컴포넌트 별로 시간 오차가 발생하는 상황에서 시간 동기화 과정이 필요하다. 안정성이 중요시되고 실시간성을 보장하고자 하는 시스템에서 동기화된 시간의 정밀도는 중요한 이슈가 되고 있는데 현재까지 제안된 시간 동기화를 그대로 사용할 경우 발생할 수 있는 딜레이 요소들로 인해 동기화된 시간의 정밀도가 떨어진다. 따라서 본 논문에서는 실제 환경에 시간 동기화가 이루어질 때 오차를 발생시키는 요소들을 지적하고 보완할 수 있는 방법들은 제안함으로써 시간 동기화의 정확도를 높인다.

• Journal of the Korea Society for Simulation
• /
• v.4 no.2
• /
• pp.31-40
• /
• 1995

A hybrid simulation model consists of real physical entities as well as simulated ones. It also contains logical processes for decision making for each operation units, a group of the entities. During the execution of such simulations, the physical and the logical processes consume real clock time while the activity durations of the simulated ones are generated. Due to the inherent chracteristics of the subjects of the communication channels. Since one can not undo an real event already taken place, the traditional central clock approach is used for the synchronization of the events(Kim[6]). However, there are still chances of causality errors due to the randomness in the communication delays. This error is not found in the distributed pure simulations. This paper explains the error in details and proposes a prevention scheme that is simple to implement.