• The Journal of the Korea Contents Association
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• v.12 no.5
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• pp.10-21
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• 2012

The role of GPU has evolved from graphics-specific processing to general-purpose processing with the development of unified shader core architecture. Especially, execution methods for general-purpose parallel applications using GPU have been researched intensively, since the parallel hardware architecture can be utilized efficiently when the parallel applications are executed. However, current GPU architecture has limitations in executing general-purpose parallel applications, since the GPU is not specialized for general-purpose computing yet. To improve the GPU performance when general-purpose parallel applications are executed, the GPU architecture should be evolved. In this work, we analyze the GPU performance according to the architecture varying the number of cores and clock frequency. Our simulation results show that the GPU performance improves by up to 125.8% and 16.2% as the number of cores increases and the clock frequency increases, respectively. However, note that the improvement of the GPU performance is saturated even though the number of cores increases and the clock frequency increases continuously, since the data cannot be provided to the GPU due to the limit of memory bandwidth. Consequently, to accomplish high performance effectiveness on GPU, computational resources must be more suitably considered.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1022-1027
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• 2003

The Motion controllers provide the sophisticated performance and enhanced capabilities we can see in the movements of robotic systems. Several types of motion controllers are available, some based on the kind of overall control system in use. PLC (Programmable Logic Controller)-based motion controllers still predominate. The many peoples use MCU (Micro Controller Unit)-based board level motion controllers and will continue to in the near-term future. These motion controllers control a variety motor system like robotic systems. Generally, They consist of large and complex circuits. PLC-based motion controller consists of high performance PLC, development tool, and application specific software. It can be cause to generate several problems that are large size and space, much cabling, and additional high coasts. MCU-based motion controller consists of memories like ROM and RAM, I/O interface ports, and decoder in order to operate MCU. Additionally, it needs DPRAM to communicate with host PC, counter to get position information of motor by using encoder signal, additional circuits to control servo, and application specific software to generate a various velocity profiles. It can be causes to generate several problems that are overall system complexity, large size and space, much cabling, large power consumption and additional high costs. Also, it needs much times to calculate velocity profile because of generating by software method and don't generate various velocity profiles like arbitrary velocity profile. Therefore, It is hard to generate expected various velocity profiles. And further, to embed real-time OS (Operating System) is considered for more reliable motion control. In this paper, the structure of chip-based precision motion controller is proposed to solve above-mentioned problems of control systems. This proposed motion controller is designed with a FPGA (Field Programmable Gate Arrays) by using the VHDL (Very high speed integrated circuit Hardware Description Language) and Handel-C that is program language for deign hardware. This motion controller consists of Velocity Profile Generator (VPG) part to generate expected various velocity profiles, PCI Interface part to communicate with host PC, Feedback Counter part to get position information by using encoder signal, Clock Generator to generate expected various clock signal, Controller part to control position of motor with generated velocity profile and position information, and Data Converter part to convert and transmit compatible data to D/A converter.

• Journal of Positioning, Navigation, and Timing
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• v.6 no.3
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• pp.125-133
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• 2017

Time comparison is necessary for the verification and synchronization of the clock. Two-way satellite time and frequency (TWSTFT) is a method for time comparison over long distances. This method includes errors such as atmospheric effects, satellite motion, and environmental conditions. Ionospheric delay is one of the significant time comparison error in case of the carrier-phase TWSTFT (TWCP). Global Ionosphere Map (GIM) from Center for Orbit Determination in Europe (CODE) is used to compare with Bernese. Thin shell model of the ionosphere is used for the calculation of the Ionosphere Pierce Point (IPP) between stations and a GEO satellite. Korea Research Institute of Standards and Science (KRISS) and Koganei (KGNI) stations are used, and the analysis is conducted at 29 January 2017. Vertical Total Electron Content (VTEC) which is generated by Bernese at the latitude and longitude of the receiver by processing a Receiver Independent Exchange (RINEX) observation file that is generated from the receiver has demonstrated adequacy by showing similar variation trends with the CODE GIM. Bernese also has showed the capability to produce high resolution IONosphere map EXchange (IONEX) data compared to the CODE GIM. At each station IPP, VTEC difference in two stations showed absolute maximum 3.3 and 2.3 Total Electron Content Unit (TECU) in Bernese and GIM, respectively. The ionospheric delay of the TWCP has showed maximum 5.69 and 2.54 ps from Bernese and CODE GIM, respectively. Bernese could correct up to 6.29 ps in ionospheric delay rather than using CODE GIM. The peak-to-peak value of the ionospheric delay for TWCP in Bernese is about 10 ps, and this has to be eliminated to get high precision TWCP results. The $10^{-16}$ level uncertainty of atomic clock corresponds to 10 ps for 1 day averaging time, so time synchronization performance needs less than 10 ps. Current time synchronization of a satellite and ground station is about 2 ns level, but the smaller required performance, like less than 1 ns, the better. In this perspective, since the ionospheric delay could exceed over 100 ps in a long baseline different from this short baseline case, the elimination of the ionospheric delay is thought to be important for more high precision time synchronization of a satellite and ground station. This paper showed detailed method how to eliminate ionospheric delay for TWCP, and a specific case is applied by using this technique. Anyone could apply this method to establish high precision TWCP capability, and it is possible to use other software such as GIPSYOASIS and GPSTk. This TWCP could be applied in the high precision atomic clocks and used in the ground stations of the future domestic satellite navigation system.

• Journal of Broadcast Engineering
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• v.21 no.6
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• pp.944-956
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• 2016

In this paper, we propose a new hardware architecture to generate computer-generated holograms based on the block based calculation method and implement a VLSI (very large scaled integrated circuit) in ASIC (application specific integrated circuit) environment. The proposed hardware has a structure that can produce a part of a hologram in the unit of a block in parallel. After calculating a block of a hologram by using an object point, the calculation is repeated to all object points and intermediate results from them are accumulated to produce a final block of a hologram. Through this structure, we can make various size of holograms with the optimized memory access in real-time operation. The proposed hardware was implemented in the Hynix 0.18um CMOS technology of Magna chip Inc. and has 876,608 gate counts. It can generate complex holograms unlike the previous researches and stably operate in the clock frequency of 200MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.12
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• pp.2731-2740
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• 2012

ASIC(application specific integrated circuit) process is a set of various technologies for fabricating a chip. Generally there have been many researches for RTL design, synthesis, floor plan & routing, low power scheme, clock tree synthesis, and testability which are widely researched in recent. In this paper we propose a new methodology of power strap routing in basis of design experience and experiment. First the power strap for vertical VDD and VSS and horizontal VDD and VSS is routed, and then after the problems which are generated in this process are analyzed, we propose a new process for resolving them. For this, the strap guide is inserted to protect the unnecessary strap routing and dumped for next steps. Next the unnecessary power straps which are generated the first inserting process are removed, and the pre-routing is performed for the macro cells. Finally the resultant power straps are routed using the dumped routing guide. Through the proposed process we identified the efficient and stable route of the power straps.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.8
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• pp.3976-3982
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• 2013

This paper presents a temperature analysis of the chaotic behavior in the voltage controlled CMOS chaotic circuit. The circuit is based on a simple nonlinear function block which is needed for chaotic signal generation. It consists of a NFB (nonlinear function block), a level shifter and non-overlapping two-phase clock for sample and hold. By SPICE simulation, chaotic dynamics such as frequency spectra and bifurcations according to the temperature variations were analyzed. And, it was showed that the circuit can generate discrete chaotic signals within control voltage in the range from 1.2 V to 2.3 V in a specific temperature condition of $25^{\circ}C$.

• ETRI Journal
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• v.34 no.1
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• pp.17-23
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• 2012

This paper analyzes the feasibility of a new 3DTV broadcasting service scenario via Advanced Television Systems Committee Mobile/Handheld (ATSC-M/H). We suggest a dual-channel system in which a left-view image is encoded by MPEG-2 with HD quality and a small-sized right-view image is encoded by AVC. Also, the left view is transmitted through ATSC main channel and the right view is transmitted through ATSC-M/H channel. Although the transport stream formats of two channels are different from each other, we demonstrate that it is possible for the ATSC 2.0 decoder to synchronize the display of the left and right views when both encoders use a common wall clock and time stamp. We also propose a program specific information descriptor which guarantees full compatibility with the conventional 2D HDTV and emerging mobile TV services. Finally, we provide the results of subjective visual quality assessment of the proposed system in support of its 3DTV service quality.

• Journal of Yeungnam Medical Science
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• v.2 no.1
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• pp.77-80
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• 1985

The R-R interval analyzer was developed to measure the autonomic nervous system function using microcomputer. The system based on 8 bit microcomputer including bandpass filter, R-wave detector and clock generator in order to obtain the mean value, standard deviation, total time, CV value, maximum value and minimum value in the specific view point of R-R interval variation. The pattern of R-R interval change after resting, voluntary standing and deep breathing can be analysed in normal subjects and diabetics with autonomic nervous dysfunction. The amplitude of the R-R interval variation showed sensitive pattern for normal subjects at resting, standing and deep breathing. On the contrary, the periodicities of amplitude for abnormal subjects with autonomic nervous dysfunction showed dull pattern. It was suggested that R-R interval analyzer is a good detection method for dysfunction of autonomic nervous system.

• Korean Journal of Radiology
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• v.24 no.10
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• pp.952-959
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• 2023

Large language models (LLMs) such as ChatGPT have garnered considerable interest for their potential to aid non-native English-speaking researchers. These models can function as personal, round-the-clock English tutors, akin to how Prometheus in Greek mythology bestowed fire upon humans for their advancement. LLMs can be particularly helpful for non-native researchers in writing the Introduction and Discussion sections of manuscripts, where they often encounter challenges. However, using LLMs to generate text for research manuscripts entails concerns such as hallucination, plagiarism, and privacy issues; to mitigate these risks, authors should verify the accuracy of generated content, employ text similarity detectors, and avoid inputting sensitive information into their prompts. Consequently, it may be more prudent to utilize LLMs for editing and refining text rather than generating large portions of text. Journal policies concerning the use of LLMs vary, but transparency in disclosing artificial intelligence tool usage is emphasized. This paper aims to summarize how LLMs can lower the barrier to academic writing in English, enabling researchers to concentrate on domain-specific research, provided they are used responsibly and cautiously.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2005.11a
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• pp.353-356
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• 2005

In this paper, the proposed $gamma({\gamma})$ line system is developed for reducing the error between non-linear gamma curve produced by a formula and result produced by hardware implementation. The proposed algorithm and system is based on the specific gamma value 2.2, namely the formula is represented by {0,1}$^{2.2}$ and the bit width of input and out data is 10bit. In order to reduce the error, the system is using least squares polynomial of the numerical method which is calculating the best fitting polynomial through a set of points. The proposed gamma line is consisting of nine kinds of quadratic equations, each with their own overlap sections to get more precise. Based on the algorithm verified by $MATLAB^{TM}$ 7.0, the proposed system is implemented by using Verilog-HDL. The proposed system has 2 clock latency; 1 result per clock. The error range (LSB) is -4 and +3. Its standard deviation is 1.287956238. The total gate count of system is 2,083 gates and the maximum timing is 15.56[ns].