• Title/Summary/Keyword: Clock Selection

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A Fully Differential RC Calibrator for Accurate Cut-off Frequency of a Programmable Channel Selection Filter

  • Nam, Ilku;Choi, Chihoon;Lee, Ockgoo;Moon, Hyunwon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.5
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    • pp.682-686
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    • 2016
  • A fully differential RC calibrator for accurate cut-off frequency of a programmable channel selection filter is proposed. The proposed RC calibrator consists of an RC timer, clock generator, synchronous counter, digital comparator, and control block. To verify the proposed RC calibrator, a six-order Chebyshev programmable low-pass filter with adjustable 3 dB cut-off frequency, which is controlled by the proposed RC calibrator, was implemented in a $0.18-{\mu}m$ CMOS technology. The channel selection filter with the proposed RC calibrator draws 1.8 mA from a 1.8 V supply voltage and the measured 3 dB cut-off frequencies of the channel selection LPF is controlled accurately by the RC calibrator.

A CMOS 5.4/3.24-Gbps Dual-Rate CDR with Enhanced Quarter-Rate Linear Phase Detector

  • Yoo, Jae-Wook;Kim, Tae-Ho;Kim, Dong-Kyun;Kang, Jin-Ku
    • ETRI Journal
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    • v.33 no.5
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    • pp.752-758
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    • 2011
  • This paper presents a clock and data recovery circuit that supports dual data rates of 5.4 Gbps and 3.24 Gbps for DisplayPort v1.2 sink device. A quarter-rate linear phase detector (PD) is used in order to mitigate high speed circuit design effort. The proposed linear PD results in better jitter performance by increasing up and down pulse widths of the PD and removes dead-zone problem of charge pump circuit. A voltage-controlled oscillator is designed with a 'Mode' switching control for frequency selection. The measured RMS jitter of recovered clock signal is 2.92 ps, and the peak-to-peak jitter is 24.89 ps under $2^{31}-1$ bit-long pseudo-random bit sequence at the bitrate of 5.4 Gbps. The chip area is 1.0 mm${\times}$1.3 mm, and the power consumption is 117 mW from a 1.8 V supply using 0.18 ${\mu}m$ CMOS process.

Method of Master Receiver Selection Using DOP for Time Synchronization in TDOA-Based Localization (TDOA 기반 위치탐지를 위한 DOP을 이용한 시각동기화 주수신기 선택 기법)

  • Kim, Sanhae;Song, Kyuha;Kwak, Hyungyu
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.41 no.9
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    • pp.1069-1080
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    • 2016
  • TDOA(Time Difference Of Arrival)-based localization system such as the passive surveillance system performs the time synchronization between the receivers after separated installing multiple receivers to set the same clock for all receivers. And it estimates 2D(or 3D) location of the target by solving intersection of the multiple hyperbola(or hyperboloid) using TDOA. To perform time synchronization, one receiver must be set to the master, and it provide the reference data to compensate the clock of the rest of the slaves. The positioning accuracy of TDOA-based localization system is changed in accordance with the master that is selected among multiple receivers. So, the optimum receiver which is selected among multiple receivers must be set to master to get best performance in the considered deployment of receivers. In this paper, we propose a selection scheme of master receiver for time synchronization using DOP(Dilution Of Precision) which is based on location of the target and the multiple receivers. The proposed scheme has low complexity and short processing time, and it is easy to automate in the TDOA-based localization systems.

A design of automatic trading system by dynamic symbol using global variables (전역 변수를 이용한 유동 심볼 자동 주문 시스템의 설계)

  • Ko, Young Hoon;Kim, Yoon Sang
    • Journal of Korea Society of Digital Industry and Information Management
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    • v.6 no.3
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    • pp.211-219
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    • 2010
  • This paper designs the dynamic symbol automatic trading system in Korean option market. This system is based on Multichart program which is convenient and efficient system trading tool. But the Multichart has an important restriction which has only one constant symbol per chart. This restriction causes very useful strategies impossible. The proposed design uses global variables, signal chart selection and position order exchange. So an automatic trading system with dynamic symbol works on Multichart program. To verify the proposed system, BS(Buythensell)-SB(Sellthenbuy) strategies are tested which uses the change of open-interest of stock index futures within a day. These strategies buy both call and put option in ATM at start candle and liquidate all at 12 o'clock and then sell both call and put option in ATM at 12 o'clock and also liquidate all at 14:40. From 23 March 2009 to 31 May 2010, 301-trading days, is adopted for experiment. As a result, the average daily profit rate of this simple strategies riches 1.09%. This profit rate is up to eight times of commision price which is 0.15 % per option trade. If the method which raises the profitable rate of wining trade or lower commission than 0.15% is found, these strategies make fascinated lossless trading system which is based on the proposed dynamic symbol automatic trading system.

A Dual Charge Pump PLL-based Clock Generator with Power Down Schemes for Low Power Systems (저 전력 시스템을 위한 파워다운 구조를 가지는 이중 전하 펌프 PLL 기반 클록 발생기)

  • Ha, Jong-Chan;Hwang, Tae-Jin;Wee, Jae-Kyung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.11
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    • pp.9-16
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    • 2005
  • This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

Transareolar-Perinipple Dual Pockets Breast Augmentation (횡유륜 유두주위절개를 통한 이중포켓 유방확대술)

  • Lee, Paik Kwon;Kim, Jee Hoon;Seo, Byung Chul;Oh, Deuk Young;Rhie, Jong Won;Ahn, Snag Tae
    • Archives of Plastic Surgery
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    • v.34 no.1
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    • pp.93-98
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    • 2007
  • Purpose: Many options are available for the incision and pocket selection in breast augmentation. Each method has its advantages and disadvantages. To leave an invisible operation scar and to achieve easier pocket dissection by the central location of the incision on the breast, we made a transareolar-perinipple incision. To overcome the disadvantages of the transareolar incision, originally advocated by Pitanguy in 1973, we modified the direction of incision line and dissection plane. Methods: To avoid the injury of 4th intercostal nerve responsible for nipple sensation, we made perinipple incision on the medial side of the nipple instead of trans-nipple incision and made the transareolar incision as 11-5 o'clock on the left side and 1-7 o'clock on the right side instead of 3-9 o'clock on both sides. To avoid the possible infection and breast feeding problem caused by the injury to the lactiferous duct, and the possible implant hernia caused by the incisions lying on a same plane of pocket dissection, we made a subcutaneous dissection just above the breast tissue medially down to the bottom of breast tissue and made a subglandular or subfascial pocket, which may avoid the injury of lactiferous duct and create different planes for skin incision and pocket dissection. Other advantages of the transareolar-perinipple incision include easier pocket dissection, less chance of hematoma, and as a result less postoperative pain because of the central location of the approach which allow finger dissection and meticulous bleeding control with direct vision, without any specialized instrument such as an endoscope or long mammary dissectors. As for pocket selection, we made dual pockets. We prefer subglandular or subfascial pocket. Also, we made a subpectoral pocket in the upper 1/4 of the pocket to add more volume on the upper part of the augmented breast, which can make aesthetically more desirable breasts in thin Asian women with small breasts. Possible disadvantages of our method are subclinical infection and scar widening, which could be overcome by meticulous operation techniques, antibiotic therapy, and intradermal tattooing. Results: From September, 2003 to August, 2005, 12 patients underwent breast augmentation using round smooth surface saline implants by our method. During the mean follow-up period of 13 months, there were no complications such as infection, hematoma, capsular contracture, and sensory change of nipple, and results were satisfactory. Conclusion: We suggest breast augmentation via transareolar-perinipple incision and dual pockets(subpectoral-subglandular or subfascial) as a valuable method in thin oriental women with small breasts.

A Design and Fabrication of the High-Speed Division/square-Root using a Redundant Floating Point Binary Number (고속 여분 부동 소수점 이진수의 제산/스퀘어-루트 설계 및 제작)

  • 김종섭;이종화;조상복
    • Proceedings of the IEEK Conference
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    • 2001.06b
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    • pp.365-368
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    • 2001
  • This paper described a design and implementation of the division/square-root for a redundant floating point binary number using high-speed quotient selector. This division/square-root used the method of a redundant binary addition with 25MHz clock speed. The addition of two numbers can be performed in a constant time independent of the word length since carry propagation can be eliminated. We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in each iterative step. It peformed the division and square-root by a redundant binary addition to the shifted binary number every 16 cycles. Also the circuit uses the nonrestoring method to obtain a quotient. The quotient selection logic used a leading three digits of partial remainders in order to be implemented in a simple circuit. As a result, the performance of the proposed scheme is further enhanced in the speed of operation process by applying new quotient selection addition logic which can be parallelly process the quotient decision field. It showed the speed-up of 13% faster than previously presented schemes used the same algorithms.

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Energy Efficiency Enhancement of TICK -based Fuzzy Logic for Selecting Forwarding Nodes in WSNs

  • Ashraf, Muhammad;Cho, Tae Ho
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.12 no.9
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    • pp.4271-4294
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    • 2018
  • Communication cost is the most important factor in Wireless Sensor Networks (WSNs), as exchanging control keying messages consumes a large amount of energy from the constituent sensor nodes. Time-based Dynamic Keying and En-Route Filtering (TICK) can reduce the communication costs by utilizing local time values of the en-route nodes to generate one-time dynamic keys that are used to encrypt reports in a manner that further avoids the regular keying or re-keying of messages. Although TICK is more energy efficient, it employs no re-encryption operation strategy that cannot determine whether a healthy report might be considered as malicious if the clock drift between the source node and the forwarding node is too large. Secure SOurce-BAsed Loose Synchronization (SOBAS) employs a selective encryption en-route in which fixed nodes are selected to re-encrypt the data. Therefore, the selection of encryption nodes is non-adaptive, and the dynamic network conditions (i.e., The residual energy of en-route nodes, hop count, and false positive rate) are also not focused in SOBAS. We propose an energy efficient selection of re-encryption nodes based on fuzzy logic. Simulation results indicate that the proposed method achieves better energy conservation at the en-route nodes along the path when compared to TICK and SOBAS.

Design of Bluetooth baseband System (블루투스 기저대역 시스템 설계)

  • 백은창;조현묵
    • Journal of Korea Multimedia Society
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    • v.5 no.2
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    • pp.206-214
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    • 2002
  • In this paper, it is designed and verified the baseband system that performs various protocol functions of specification of the Bluetooth system. In order to verify the developed circuits, various baseband functions are tested by using the ModelSim simulator. The developed circuits operate at 4MHz main clock. Test suite includes hap selection function, generation of the sync word, error correction(1/3 rate FEC, 2/3 rate FEC), HEC generation/checking, CRC generation/checking, data whitening/dewhitening and packet trans/reception procedure. etc. As a result of the simulation, it is verified that the developed baseband system conform to the specification of the Bluetooth system.

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Selection Methods of Multi-Constellation SBAS in WAAS-EGNOS Overlap Region (WAAS-EGNOS 중첩 영역 내 위성기반 보강시스템 선택 기법 연구)

  • Kim, Mingyu;Kim, Jeongrae
    • Journal of Advanced Navigation Technology
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    • v.23 no.3
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    • pp.237-244
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    • 2019
  • Since SBAS provides users with GNSS orbit, clock, and ionospheric corrections and integrity, the more precise positioning is possible. As the SBAS service area is expanded due to the development of the SBAS and the installation of the additional ground stations, there is a region where two or more SBAS messages can be received. However, the research on multi-constellation SBAS selection method has not carried out. In this study, we compared the result of positioning accuracy after applying the SBAS correction selected by using WAAS priority, EGNOS priority, or error covariance comparison method to LEO satellites in the regions where WAAS and EGNOS signals are transmitted simultaneously. When using WAAS priority method, 3D orbit error is smallest at 2.57 m. The covariance comparison method is outperform at the center of the overlap region far from each WAAS and EGNOS stations. In the eastern region near the EGNOS stations, the 3D orbit errors using EGNOS priority method is 8% smaller than the errors using the WAAS priority method.