• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.5
• /
• pp.1304-1316
• /
• 1996

In this paper, A VCO(Voltage Controlled Oscillator) in use of clock recovery/data regeneration circuit for 10 Gbps fiber optic receivers was developed. The improved hair-pin resonator with a parallel coupled lines, which has been applied to microstrip filters, was used as a resonance part. As a frequcncy tuning device by substituting 3-terminalMESFET vaaractor for varactor diode, an MMIC manufacturing process will be simplified. Since a hair-pin resonator is planar type compared to the dielectric resonator and has a relatively flat reactance verus frequency, it will be favorable to apply a hair-pin resonator to an MMIC, in addition wideband frequency tuning range is able to be obtained.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
• /
• 2002.11a
• /
• pp.394-397
• /
• 2002

A design study of phase detectors for the 2.5 Gb/s CDR circuit using a standard 0.18-${\mu}{\textrm}{m}$ CMOS process has been performed. The targeted CDR is based on the phase-locked loop and thus it consists of a phase detector, a charge pump, a LPF, and a VCO. For high frequency operation of 2.5 Gb/s, phase detector and charge pump, which accurately compare phase errors to reduce clock jitter, are critical for designing a reliable CDR circuit. As a phase detector, the Hogge phase detector is selected but two transistors are added to improve the performance of the D-F/F. The charge pump was also designed to be placed indirectly input and output.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.3 no.4
• /
• pp.194-198
• /
• 2003

A 16-bit adiabatic low-power Micro-processor core is designed. The processor consists of control block, multi-port register file and ALU. A simplified four-phase clock generator is designed to provide supply clocks for adiabatic processor. All the clock line charge on the capacitive interconnections is recovered to recycle the energy. Adiabatic circuits are designed based on ECRL(efficient charge recovery logic) and $0.35\mu\textrm$ CMOS technology is used. Simulation results show that the power consumption of the adiabatic Microprocessor core is reduced by a factor of 2.9~3.1 compared to that of conventional CMOS Microprocessor

• Journal of IKEEE
• /
• v.13 no.2
• /
• pp.118-125
• /
• 2009

With recent advancement of high-speed, multi-gigabit data transmission capabilities, transmitters usually send data without clock signals for reduction of hardware complexity, power consumption, and cost. Therefore clock and data recovery circuits(CDR) become important to recover the clock and data signals and have been widely studied. This paper presents the design of 10Gbps CDR in 0.18$\mu$m CMOS process. A quarter-rate bang-bang phase detector is designed to reduce the power and circuit complexity, and a 4-stage LC-type VCO is used to improve the jitter characteristics. Simulation results show that the designed CDR consumes 80mW from a 1.8V supply, and exhibits a peak-to-peak jitter of 2.2ps in the recovered clock. The chip layout area excluding pads is 1.26mm$\times$1.05mm.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.22 no.8
• /
• pp.1765-1773
• /
• 1997

The communication systems which include PLL may have cycle clip problem because of channel noise. The cycle slip problem occurs the synchronization loss of communication system and it may be fatal to the synchronous stream cipher system. While continuous resynchronization is used to lessen the risk of synchronization it has some problems. In this paper, we propose the method which solve the problems by using continuous resynchronization with the clock recovery technique. If the counted value of real clock pulse in reference duration is not same as that of normal state, we decide the cycle slip has occurred. The damaged clock by cycle slip is compensated by adding or subtracting the clock pulse according to the type of cycle slip. It reduced the time for resynchronization by twenty times. It means that 17.8% of data for transmit is compressed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 1998.11a
• /
• pp.257-262
• /
• 1998

본 논문에서는 DSP(Digital Signal Processor)를 이용해 INMARSAT-M 위성통신용 단말기 중의 변ㆍ복조부를 설계하였다. R-RC(ROOt Raised Cosine) 필터에 의해 대역제한된 OQPSK 파형의 발생과 디지털 정합필터(Matched filter)를 이용한 OQPSK 복조, 부호율 1/2이고 구속장이 7인 길쌈부호기 및 클록 복구(Clock recovery)의 구현 알고리즘을 C언어와 어셈블리어로 작성하고, 모뎀을 실제 제작하여 변조기능, 복조기능으로 나누어서 동작 특성을 살펴보았다.

• Electronics and Telecommunications Trends
• /
• v.13 no.2 s.50
• /
• pp.1-9
• /
• 1998

고속 광 시스템에서 필요로 하는 광 재생 중계기, 시간 분할 스위칭 시스템이나 다중 분리화 회로 및 클럭 재생 기술이 필수적이다. 본 고에서는 고주파수 광 클럭 추출을 구현하기 위해서 활발히 진행되고 있는 광 클럭 재생 기술의 최근 개발 동향을 분석해 보고자 한다. 아직은 어느 하나도 완벽한 방법이라 할 수 없겠지만, 각 방법의 장단점을 헤아려 보고 구성하고자 하는 통신망에 적절한 광 클럭 재생기술을 채택하여 사용하는 것이 필요하리라 본다.

• Proceedings of the Optical Society of Korea Conference
• /
• 2001.02a
• /
• pp.74-75
• /
• 2001

현재의 통신망에서는 clock recovery, regeneration 등을 전기적으로 처리하고 있으나 처리속도의 한계가 있고, 미래의 초고속 네트웍은 이러한 전기적 신호처리의 속도한계를 극복하는 기술이 필요하다. 그러므로, 고속의 광교환과 광신호처리 등 광신호를 전기적으로 바꾸거나 제어하지 않고 전광으로 처리하는 기술에 대한 연구가 진행되고 있으며 이러한 전광신호 처리에 고속의 전광 논리소자가 요구된다. 초기의 전광 논리소자 연구에서는 AND, OR, NOR, XOR 등의 기본 논리 기능이 주로 구현되었으며 이를 활용하여 Shift Register, Binary counter, 전광 반가산기, 직/병렬 데이터 변환기와 같은 복합기능 논리소자의 구현 연구가 이루어지고 있다. (중략)

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.2
• /
• pp.64-70
• /
• 2009

A 6-Gbps feed-forward equalizer having a 6.2-dB gain at 3GHz is designed in 0.13-um CMOS technology and the equalizer helps error-free data recovery over a 7-m SATA cable with 14.7dB loss. Based on a differentially-connected varactor, the proposed equalizer uses only a one-fourth varactor size of a conventional equalizer, which enables the equalizer's integration in a pad-frame, high operating frequency, and low power dissipation of 3.6mW.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.4
• /
• pp.78-83
• /
• 1996

A timing recovery circuit of 10 Gbit/s optical receiver is described. The circuit consists of a passive NRZ-to-PRZ circuit, a dielectric resonator filter (DRF) and a narrow band amplifier, which for the first time adopted a temperature compensation technique using the tempareature characteristics of DR. The experimental results showed an output clock phase variation of less than ${\pm}$6 degree over the operating temperature range form 0$^{\circ}C$ to 75$^{\circ}C$ and measured maximum rms jitters of less than 2 phs with the resonance detunings of up to ${\pm}$10 MHz. These experimental results show that the circuit is a suitable for 10 Gbit/s lightwave transmission system.