• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.39 no.3
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• pp.225-231
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• 2011

The satellite clock anomalies, one of the abnormal signal factors of the GPS satellites, can have a significant impact on the GPS measurements. However, it can be difficult to detect the anomalies of the satellites clock before the range of the satellites clock error becomes bigger than the range of the other factors, due to the measurement including error of the orbit, ionosphere delay, troposphere delay, multipath and receiver clock. In order to perform quick and accurate detection by minimization of critical range in anomalies of the satellites clock, this paper suggested a solution to detect precise anomalies of the satellites clock after application of carrier smoothing filter from measurement by dual-frequency and adjustment of errors which can be occurred by other factor and the receiver clock errors. The performance of the proposed method was confirmed by comparing to the satellite clock biases which are provided by IGS.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.99-108
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• 2015

The embedded microcontroller which is operated by the logic gates synchronized on the clock pulse, is gradually used as main controller of mission-critical systems. Severe electrical situations such as high voltage/frequency surge may cause malfunctioning of the clock source. The tolerant system operation is required against the various external electric noise and means the robust design technique is becoming more important issue in system clock failure problems. In this paper, we propose on-chip backup clock change architecture for the automatic clock failure detection. For the this, we adopt the edge detector, noise canceller logic and glitch-free clock changer circuit. The implemented edge detector unit detects the abnormal low-frequency of the clock source and the delay chain circuit of the clock pulse by the noise canceller can cancel out the glitch clock. The externally invalid clock source by detecting the emergency status will be switched to back-up clock source by glitch-free clock changer circuit. The proposed circuits are evaluated by Verilog simulation and the fabricated IC is validated by using test equipment electrical field radiation noise

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.11-22
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• 2016

Clock skew scheduling is one of the essential steps to be carefully performed during the design process. This work addresses the clock skew optimization problem integrated with the consideration of the inter-dependent relation between the setup and hold times, and clock to-Q delay of flip-flops, so that the time margin is more accurately and reliably set aside over that of the previous methods, which have never taken the integrated problem into account. Precisely, based on an accurate flexible model of setup time, hold time, and clock-to-Q delay, we propose a stepwise clock skew scheduling technique in which at each iteration, the worst slack of setup and hold times is systematically and incrementally relaxed to maximally extend the time margin. The effectiveness of the proposed method is shown through experiments with benchmark circuits, demonstrating that our method relaxes the worst slack of circuits, so that the clock period ($T_{clk}$) is shortened by 4.2% on average, namely the clock speed is improved from 369 MHz~2.23 GHz to 385 MHz~2.33 GHz with no time violation. In addition, it reduces the total numbers of setup and hold time violations by 27.7%, 9.5%, and 6.7% when the clock periods are set to 95%, 90%, and 85% of the value of Tclk, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.74-80
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• 2002

VLSI intergrated circuits like SOC(system on chip) often require a multi-clock design style for functional or performance reasons. The problems of the clock domain transition due to clock skew and clock ordering within a test cycle may result in wrong results. This paper describes a new BIST(Built-in Self Test) architecture for multi-clock systems. In the new scheme, a clock skew is eliminated by a multi-capture. Therfore, it is possible to perform at-speed test for both clock inter-domain and clock intra-domain.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.11
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• pp.1-9
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• 1996

In the following paper, new architectural algorithm of clock and data recovery circuit is proposed for 622.08 Mbps optical communication receiver. New algorithm makes use of charge pump PLL using voltage controlled ring oscillator and extracts 8-channel 77.76 MHz clock signals, which are delayed by i/8 (i=1,2, ...8), to convert and recover 8-channel parallel data from 662.08 Mbps MRZ serial data. This circuit includes clock genration block to produce clock signals continuously even if input data doesn't exist. And synchronization of data and clock is doen by the method which compares 1/2 bit delayed onput data and decided dta by extracted clock signals. Thus, we can stabilize frequency and phase of clock signal even if input data is distorted or doesn't exist and simplify receiver architecture compared to traditional receiver's. Also it is possible ot realize clock extraction, data decision and conversion simulataneously. Verification of this algorithm is executed by DESIGN CENTER (version 6.1) using test models which are modelized by analog behavior modeling and digital circuit model, modified to process input frequency sufficiently, in SPICE.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.394-397
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• 2003

In this paper, we have proposed a clock recovery algorithm of OFDM/QPSK-DMR(Orthogonal Frequency Division Multiplexing/Quadrature Phase Shift Keying Modulation-Digital Microwave Radio)system using BL-PSF(Band Limited-Pulse Shaping Filter) and have analyzed the clock phase error variance performance of OFDM/QPSK and single carrier DMR systems. The existing OFDM/QPSK-DMR system using the windowing requires training sequence or CP(Cyclic Prefix) to synchronize a receiver clock frequency Because there is no training sequence or CP(Cyclic prefix) in our proposed DMR system, the proposed clock recovery algorithm is useful to the OFDM/QPSK-DMR system using BL-PSF, The simulation results confirm that the proposed clock recovery algorithm has the same clock phase error variance performance in a single carrier DMR system under AWGN(Additive White Gaussian Noise) environment.

• Journal of Technologic Dentistry
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• v.7 no.1
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• pp.5-12
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• 1985

This experimental study is perform to study the effect of the direction for the centrifugal force in operating centrifugal casting machine. In order to investigate the effect of direction for centrifugal force action on the casting ability 20 pieces of specimen are produced including one vertical direction and four horizontal directions. Casting shows us that the 15 pieces of specimen among them are included within $\pm$16. The results obtained through the comparison with 5 groups of the casting ability are as follows: 1. In the experiment of the casting, statistically significant difference are found between the vertical direction and the group of horizontal direction, namely, the direction of 3, 6, 9 and 12 o'clock, and also statistically there are significant differences between the direction of 9 o'clock and of 6 o'clock, and between the direction of 9 o'clock and of 12 o'clock which lie between the groups of horizontal directions. 2. The degree of casting ability is showing us on an average, 23.80 in the vertical direction. And also in the group of horizontal direction it prove in turn 15.60 in the direction of 9 o'clock, 14.47 of 3 o'clock, 13.30 of 12 o'clock, and 12.80 of 6 o'clock.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.36 no.6
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• pp.621-628
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• 2018

More than four visible GPS (Global Positioning System) satellites are required to obtain absolute positioning. However, it is not easy to satisfy this condition when a rover is in such unfavorable condition as an urban area. As a consequence, clock-aided positioning has been used as an alternative method especially when the number of visible satellites is three providing that receive clock error information is available. In this study, LSC (Least-Squares Collocation) method is proposed to interpolate clock errors for clock-aided positioning after analyzing the characteristics of receiver clock errors. Numerical tests are performed by using GPS data collected at one of Korean CORS (Continuously Operating Reference Station) and a nearby GPS station. The receiver clock errors are obtained through the DGPS (Differential GPS) positioning technique and segmentation procedures are applied for efficient interpolation. Then, LSC is applied to predicted clock error at epoch which clock information is not available. The numerical test results are analyzed by examining the differences between the original and interpolated clock errors. The mean and standard deviation of the residuals are 0.24m and 0.49m, respectively. Therefore, it can be concluded that sufficient accuracy can be obtained by using the proposed method in this study.

• Journal of IKEEE
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• v.23 no.3
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• pp.858-864
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• 2019

A clock system is proposed to eliminate data loss due to frequency difference between sensor nodes in a sensor utility network. The proposed clock system for each sensor node consists of a bust clock-data recovery (CDR) circuit, a digital phase-locked loop outputting a 32-phase clock, and a digital frequency synthesizer using a programmable open-loop fractional divider. A CMOS oscillator using an active inductor is used instead of a burst CDR circuit for the first sensor node. The proposed clock system is designed by using a 65 nm CMOS process with a 1.2 V supply voltage. When the frequency error between the sensor nodes is 1%, the proposed burst CDR has a time jitter of only 4.95 ns with a frequency multiplied by 64 for a data rate of 5 Mbps as the reference clock. Furthermore, the frequency change of the designed digital frequency synthesizer is performed within one period of the output clock in the frequency range of 100 kHz to 320 MHz.

• ETRI Journal
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• v.30 no.2
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• pp.275-281
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• 2008

A 40 Gb/s clock and data recovery (CDR) module for a fiber-optic receiver with improved phase-locked loop (PLL) circuits has been successfully implemented. The PLL of the CDR module employs an improved D-type flip-flop frequency acquisition circuit, which helps to stabilize the CDR performance, to obtain faster frequency acquisition, and to reduce the time of recovering the lock state in the event of losing the lock state. The measured RMS jitter of the clock signal recovered from 40 Gb/s pseudo-random binary sequence ($2^{31}-1$) data by the improved PLL clock recovery module is 210 fs. The CDR module also integrates a 40 Gb/s D-FF decision circuit, demonstrating that it can produce clean retimed data using the recovered clock.