• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.6
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• pp.18-24
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• 2012

This paper reports the test results of a 50MHz/s 10 bits DAC developed with $0.18{\mu}m$ CMOS process for the wireless sensor network application. The 10bits DAC, not likely a typical segmented type, has been designed as a current driving type with double step thermometer decoding architecture in which 10bits are divided into 6bits of MSB and 4bits of LSB. MSB 6bits are converted into 3 bits row thermal codes and 3 bits column thermal codes to control high current cells, and LSB 4 bits are also converted into thermal codes to control the lower current cells. The high and the lower current cells use the same cell size while a bias circuit has been designed to make the amount of lower unit current become 1/16 of high unit current. All thermal codes are synchronized with output latches to prevent glitches on the output signals. The test results show that the DAC consumes 4.3mA DC current with 3.3V DC supply for 2.2Vpp output at 50MHz clock. The linearity characteristics of DAC are the maximum SFDR of 62.02dB, maximum DNL of 0.37 LSB, and maximum INL of 0.67 LSB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.50-55
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• 2008

In this paper, New LC VCO with $8{\sim}10.9$ GHz Band has been designed using commercial $0.35-{\mu}m$ CMOS technology. This proposed circuit is consisted of the parallel construction of the typical NMOS and PMOS cross-coupled pair which is based on the LC tank, MOS cross-coupled pair which has same tail current of complementary NMOS and PMOS, and output buffer. The designed LC VCO, which is according to proposed structure in this paper, takes a 29% improvement of the wide tuning range as 8 GHz to 10.9 GHz, and a 6.48mW of low power dissipation. Its core size is $270{\mu}m{\times}340{\mu}m$ and its phase noise is as -117dBc Hz and -137dBc Hz at 1-MHz and 10-MHz offset, respectively. FOM of the new proposed LC VCO gets -189dBc/Hz at a 1-MHz offset from a 10GHz center frequency. This design is very useful for the 10Gb/s clock generator and data recovery integrated circuit(IC) and SONET communication applications.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.78-89
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• 2013

This paper proposes a high-throughput and multi-mode quasi-cyclic (QC) low-density parity-check (LDPC) decoder based on a fully parallel structure. The proposed QC-LDPC decoder employs the fully parallel structure to provide very high throughput. The high interconnection complexity, which is the general problem in the fully parallel structure, is solved by using a broadcasting-based sum-product algorithm and proposing a low-complexity cyclic shift network. The high complexity problem, which is caused by using a large amount of check node processors and variable node processors, is solved by proposing a combined check and variable node processor (CCVP). The proposed QC-LDPC decoder can support the multi-mode decoding by proposing a routing-based interconnection network, the flexible CCVP and the flexible cyclic shift network. The proposed QC-LDPC decoder is operated at 100 MHz clock frequency. The proposed QC-LDPC decoder supports multi-mode decoding and provides 8.1 Gbps throughput for a (1944, 1620) QC-LDPC code.

• Journal of IKEEE
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• v.5 no.1 s.8
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• pp.100-110
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• 2001

In this paper, we investigated several buffer management schemes for the design of shared-memory type ATM switches, which can enhance the utilization of switch resources and can support quality-of-service (QoS) functionalities. Our results show that dynamic threshold (DT) scheme demonstrate a moderate degree of robustness close to pushout(PO) scheme, which is known to be impractical in the perspective of hardware implementation, under various traffic conditions such as traffic loads, burstyness of incoming traffic, and load non-uniformity across output ports. Next, we considered buffer management strategies to support QoS functions, which utilize parameter values obtained via connection admission control (CAC) procedures to set tile threshold values. Through simulations, we showed that the buffer management schemes adopted behave well in the sense that they can protect regulated traffic from unregulated cell traffic in allocating buffer space. In particular, it was observed that dynamic partitioning is superior in terms of QoS support than virtual partitioning.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.9
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• pp.1916-1932
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• 1997

The synchronous stream cipher which require absoulte clock synchronization has the problem of synchronization loss by cycle slip. Synchronization loss makes the state which sender and receiver can't communicate with each other and it may break the receiving system. To lessen the risk, we usually use a continuous resynchronization method which achieve resynchronization at fixed timesteps by inserting synchronization pattern and session key. While we can get resynchronization effectively by continuous resynchroniation, there are some problems. In this paper, we proposed an adaptive resynchronization algorithm for cipher system using HDLC protocol. It is able to solve the problem of the continuous resynchronization. The proposed adaptive algorithm make resynchronization only in the case that the resynchronization is occurred by analyzing the address field of HDLC. It measures the receiving rate of theaddress field in the decision duration. Because it make resynchronization only when the receiving rate is greateer than the threshold value, it is able to solve the problems of continuous resynchronization method. When the proposed adaptive algorithm is applied to the synchronous stream cipher system in packet netork, it has addvance the result in R_e and D_e.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4A
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• pp.336-344
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• 2005

Discrete Wavelet Transform(DWT) is the oncoming generation of compression technique that has been selected for MPEG4 and JEPG2000, because it has no blocking effects and efficiently determines frequency property of temporary time. In this paper, we propose an efficient bit-serial architecture for the low-power and low-complexity DWT filter, employing two-channel QMF(Qudracture Mirror Filter) PR(Perfect Reconstruction) lattice filter. The filter consists of four lattices(filter length=8) and we determine the quantization bit for the coefficients by the fixed-length PSNR(peak-signal-to-noise ratio) analysis and propose the architecture of the bit-serial multiplier with the fixed coefficient. The CSD encoding for the coefficients is adopted to minimize the number of non-zero bits, thus reduces the hardware complexity. The proposed folded 1D DWT architecture processes the other resolution levels during idle periods by decimations and its efficient scheduling is proposed. The proposed architecture requires only flip-flops and full-adders. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a Hynix 0.35$\mu$m STD cell library. The maximum operating frequency is 200MHz and the throughput is 175Mbps with 16 clock latencies.

• Korean journal of applied entomology
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• v.27 no.2
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• pp.111-116
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• 1988

Fruit piercing moths were collected at every other at orchaed(16.5ha) planted with plum, peach and pear, and surrounded by forest in Gyeongnam province from jun to September in 1987. Four black light (BL) traps were lightened to attract the moths from sunset to sunrise and sweep net was also used to catch the moths on fruit and around fruit trees from 22 to 23 o'clock, 20 minutes per fruit tree species. Forty-one species, including 15 primary piercing species(PPS) and 22 secondary piercing species (SPS), from 3 families were collected and identified as fruit piercing moths. Among them, 16 species are newly recorded as fruit piercing moths in Korea. O. emarginata, L. juno, P. stuposa, C. lata and O. excavata were diminant species of PPS, comprising 86.7% of the whole PPS. Dominant species of SPS were A. ipsilon, M. turca, S. retorata, A. livida and T. oldenlandiae, comprising 80.5% of the whole SPS. The ratios of PPS to the whole fruit piercing moths collected by BL traps and net were sweep 15.2% and 79.7%, repectively. By sweep net L. juno, P. stuposa, and O. emarginata was also captured in a large numbers on peach, C. lata was on plum, and S. retorata was on pear.

• The Korean Journal of Zoology
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• v.38 no.4
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• pp.550-556
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• 1995

The c-myc proto-oncogene is Involved In the control of normal cell proliferation and differentiation of many cell lineages. Although it has heen suggested that c-myc may play an important role in the mammalian early development, it Is unclear whether the embryonic c-myc mRNA is originated from zygotic gene expression or stored maternal message. Thus, we have construded expression vectors, In which the 5, flanking sequences including c-myc promoter region and a large non-coding exon I are fused 'sith E. coli lacZ gene that encedes $\beta$-galactosldase as a reporter. As c-myc exon I contains a modulatory sequence, we designed t, vo types of vectors (pcmyc.Gall and pcmyc-Ga12) to examine the role of exon I in c-myc expression. The former contains the complete exon I and the later has a deletion in 40 bp of modulator sequence located In the exon I of c-myc These vectors were microInjected into fertilized one-cell embryos and $\beta$-galactosidase activity was examined by X-gal staining during early embryogenesis. $\beta$-galactosidase activity derived from c-myc promoter was decreased at two-cell stage. The expression level directed by pcmyc- Ga12 was similar to that of pcmyc-Gal1, indicating that the medulatory sequence in exon I may not be Involved at least In the regulation of embryonic c-myc expression. In summary, the present study indicates that the c-myc promoter is functional at the early stage embryo, and the regulation of c-myc expression is under the control of "zygotic" clock of preimplantation mouse embryos.e embryos.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.3
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• pp.304-315
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• 2001

In this paper, we peformed the real-time implementation of AMR(Adaptive Multi-Rate) speech coding algorithm which is adopted for IMT-2000 service using TMS320C6201, i.e., a Texas Instrument´s fixed-point DSP. With the ANSI C source code released from ETSI, optimization is performed to make it run in real-time with memory as small as possible using the C compiler and assembly language. Implemented AMR speech codec has the size of 32.06 kWords program memory, 9.75 kWords data RAM memory, and 19.89 kWords data ROM memory. And, The time required for processing one frame of 20 ms length speech data is about 4.38 ms, and it is short enough for real-time operation. It is verified that the decoded result of the implemented speech codec on the DSP is identical with the PC simulation result using ANSI C code for test sequences. Also, actual sound input/output test using microphone and speaker demonstrates its proper real-time operation without distortions or delays.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.9
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• pp.13-19
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• 2008

Time synchronization of nodes in sensor network synchronizes sensor nodes to one time clock. This is very essential in sensor networks so that the information collected and reported from the sensor nodes becomes meaningful. If sensor nodes are not synchronized, disaster report with time information can be wrong analyzed and this may lead to big calamity. With the limitation of battery and computing power, time synchronization algorithm imported in sensor nodes has to be as simple as it doesn't need big complexity, nor generates many synchronization messages. To reduce the synchronization error, hop count should be kept small between reference node to initiate synchronization and sensor nodes to be synchronized. Therefore, multiple reference nodes are used instead of single reference node. The use of multiple reference nodes introduce the requirement of synchronization among reference nodes in the network. Several algorithms have been proposed till now, but the synchronization among reference nodes are not well considered. This paper proposes improved time synchronization for sensor networks by synchronizing multiple reference nodes inside the network. Through simulation, we validated the effects of new algorithm.