• Journal of Integrative Natural Science
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• v.16 no.2
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• pp.61-67
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• 2023

Human body ages differently due to environmental, genetic and pathological factors. DNA methylation patterns also differs depending on various factors such as aging and several other diseases. The aging clock model, which uses these differences to predict age, analyzes DNA methylation patterns, recognizes age-specific patterns, predicts age, and grasps the speed and degree of aging. Aging occurs in everyone and causes various problems such as deterioration of physical ability and complications. Alzheimer's disease is a disease associated with aging and the most common brain degenerative disease. This disease causes various cognitive functions disabilities such as dementia and impaired judgment to motor functions, making daily life impossible. It has been reported that the incidence and progression of this disease increase with aging, and that increased phosphorylation of Aβ and tau proteins, which are overexpressed in this disease and accelerates epigenetic aging. It has also been reported that DNA methylation is significantly increased in the hippocampus and entorhinal cortex of Alzheimer's disease patients. Therefore, we calculated the biological age using the Epi clock, a pan-tissue aging clock model, and confirmed that the epigenetic age of patients suffering from Alzheimer's disease is lower than their actual age. Also, it was confirmed to slow down aging.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.911-914
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• 2001

본 논문에서는 10Gigabit Ethernet 물리계충 전송 기술로서 IEEE 802.3 Higher Speed Study Group (HSSG)에서 검토했던 방법으로 선로부호화 방법이 있는데 그 중에서 국내 연구진에 의해 제안된 최소 대역폭 선로부호 MB810을 사용하여 10Gigabit Ethernet에서의 clock recovery 가능성에 대해 알아 본다. MB810 code를 사용하면 기존의 통신 시스템에서 필요로하는 대역폭을 반만 사용하여 전송할 수 있기 때문에 대역 효율이 좋아지나 이전의 일반적인 square law 방법으로는 clock recovery가 어렵다. 본 논문에서는 4th power law 방법을 사용했을때의 이론적인 해석과 시뮬레이션 결과를 보인다.

• Proceedings of the Korean Information Science Society Conference
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• 2001.10c
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• pp.7-9
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• 2001

ASIC 설계에서 gated clock으로 동작하는 clock을 입력으로 받는 회로들은 스캔 테스트를 수행하기에 용이하지 않다. 이러한 회로들에 대하여 스캔 테스트기법을 적용하기 위한 설계변경기술을 제안한다. 제안하는 설계변경기술은 비동기 회로를 동기 회로로 변환함으로써 스캔 기법을 적용할 수 있는 회로로 변환하게 된다. 이로써 테스트를 좀 더 용이하게 수행할 수 있을 뿐 아니라 결함 시험도를 높이게 되는 효과를 가져올 수 있다.

• 한국정보통신설비학회:학술대회논문집
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• 2009.08a
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• pp.78-80
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• 2009

In this paper, we have described the advantages of fixed mobile convergence access network based on FTTH. Also, we have investigated the possibility of mobile backhaul based on FTTH network combined TOM over IP emulation and adaptive clock recovery technologies, and verified successful transport of both E1 TDM traffic and Clock through the packet based PON network. within the allowable tolerance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.193-199
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• 2008

A combined clock and data recovery (CDR) circuit with adaptive cancellation of data-dependent jitter (DDJ) is constructed in all-digital architecture which is amenable to deep submicron technology. The DDJ canceller uses an adaptive FIR filter to compen-sate for any unknown channel characteristic. The proposed CDR decreases jitter in the recovered clock since the DDJ canceller significantly cancels out incoming jitter caused by inter-symbol interference.

• The Korean Journal of Ecology
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• v.11 no.4
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• pp.193-200
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• 1988

The amount of Pinus rigida pollen deposition was hourly measured by Durhan's pollen trap in Seoul National University during May 9∼16 o'clock and 9∼15, 1988. The peak times or pollen deposition were 9∼10 o'clock and 16∼17 o'clock. The correlation coefficients between pollen deposition and mean temperature, relative humidity, and wind speed were 0.625, -0.655 and 0.418 respectively, It is thought that pollen maturation rate is correlated with mean temperature and the pollen deposition with increasing wind speed.

• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.415-417
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• 2005

Core operations (e.9. TDMA scheduler, synchronized sleep period, data aggregation) of many proposed protocols for different layer of sensor network necessitate clock synchronization. Our Paper mingles the scheme of dynamic clustering and diffusion based asynchronous averaging algorithm for clock synchronization in sensor network. Our proposed algorithm takes the advantage of dynamic clustering and then applies asynchronous averaging algorithm for synchronization to reduce number of rounds and operations required for converging time which in turn save energy significantly than energy required in diffusion based asynchronous averaging algorithm.

• Korean Journal of Optics and Photonics
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• v.11 no.6
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• pp.400-404
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• 2000

All-optical clock recovery from a 10 Gb/s RZ signal has been demonstrated using an actively mode-locked figure-eight laser incorporating a semiconductor optical amplifier in the loop-mirror scheme. Optical pulses with 10 ps pulse width were modulated by a LiNb03 external modulator at $2^{23}-1$ PRES and injected into the clock recovery circuit to extract optical pulses with 12 ps width. Regeneration of the original bit pattern has been accomplished by modulating the recovered clock with the same modulator, and no power penalty was observed at $10^{11}$..

• Journal of the Korea Institute of Military Science and Technology
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• v.23 no.5
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• pp.516-522
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• 2020

In this paper, the frequency detector which detects the clock frequency of the embedded system is proposed and analyzed. The proposed frequency detector is consisted of filter and peak voltage detector. The clock signal is converted from square wave to triangular wave by the filter. The peak voltage of the triangular wave is determined according to the frequency response of filter. The peak voltage detector detects and holds the peak voltage of the signal. Moreover, the proposed clock frequency detector can detect the frequency within 1ms and it gives guarantee of real-time operation.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.221-225
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• 2000

We designed asynchronous event logic library with 0.25$\mu\textrm{m}$ CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6㎓. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about 1.1mm ${\times}$ 1.1mm.