• The KIPS Transactions:PartC
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• v.11C no.1
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• pp.123-134
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• 2004

The synchronized clock performance in the synchronization network and SDH transmission network design is an important element in aspect of guaranteeing network stability and data transmission. Consequently the simulator which can applicable various parameters and several input levels from the best state to the worst state for performance analysis of the synchronized clock is required in case of network design. Therefore, in this paper, 1 developed the SNCA and TNCA for analysis of the synchronized clock in the synchronization network and transmission network. And utilizing these simulators with various wander generation, node number and clock state, 1 obtained the synchronized clock characteristics and maximum network nodes In NE1, NE2 and NE3 transmission network and DOTS1, DOTS2 synchronization network.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12B
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• pp.1037-1041
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• 2004

In this paper we propose a new conceptual slave clock system in which remotely located clock is synchronized to the reference clock by intermediation of the satellite time, show a probability of adoption to real network by experiments. This new proposed method has lots of structural advantages over the existing methods because all of the node clocks can be maintained with the same hierarchical quality. The measurement results show that the accuracy of the experimental slave clock system can be kept within a few parts in 1012 and that the MTIE (Maximum Time Interval Error) meets the ITU-T Recommendation G.811 for the primary reference clock A prototype system having fully automatic operational functions has been realized, and it is expected to be commercially used as a node clock for synchronization in the digital communication network in the near future.

• 한국정보통신설비학회:학술대회논문집
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• 2005.08a
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• pp.159-165
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• 2005

The proposed optical transmitter is composed of FF(flip flop) , PLL (phase locked loop), reference clock generator, serializer and LD driver 10x250 Mb/s data arrays are translated to the 2.5 Gb/s data signal by serializer. In this case, 1 data bus is allocated usually as a reference clock for synchronization. In this proposed optical transmitter, 125 MHz reference clock is generated from 10x250 Mb/s data arrays by reference clock generator. From this method. absent of reference clock bus is available and more data transmission become possible. To achieve high speed operation, the serializer circuit is designed as two stacks. For 10:1 serialization, 10 clocks that have 1/10 lambda differences is essential, so the VCO (voltage controlled oscillator) composed of 10 delay buffers is designed. PLL is for runing at 250 MHz, and dual PFD(phase frequency detector) is adopted for fast locking time. The optical transmitter is designed by using 0.35 um CMOS technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37C no.10
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• pp.894-900
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• 2012

Indoor wireless positioning system uses ranging information of beacons in order to precisely estimate a tag location. To estimate distance between each beacons and tag, the system calculates arrival time of a tag pulse with clock of each beacon including independent clock offset. This clock offset seriously affects the performance of ranging and positioning. We propose in this paper a clock offset compensation method to solve this problem. To verify the performance of the proposed method, we simulated location estimation with random clock offset between -1,000ppm and 1,000ppm, and the result shows that the proposed scheme effectively solves the clock offset problem.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.2
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• pp.93-101
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• 2003

Scan design is a structured design-for-testability technique in which flip-flops are re-designed so that the flip-flops are chained in shift registers. The scan design cannot be used in a design with scan design rule violations without modifying the design. The most important scan design rule is concerning clock and reset signals to pins of the flip-flops or scan cells. Clock and Reset pins of every scan cell must be controllable from top-level ports. We propose a new technique to re-design gated clocks and resets which violate the scan design rule concerning the clock and reset pins. This technique substitutes synchronous sequential circuits for gated clock and reset designs, which removes the clock and reset rule violations and improves fault coverage of the design. The fault coverage is improved from $90.48\%$ to $100.00\%$, from $92.31\%$ to $100.00\%$, from $95.45\%$ to $100.00\%$, from $97.50\%$ to $100.00\%$ in a design with gated clocks and resets.

• Journal of Electrical Engineering and Technology
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• v.13 no.6
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• pp.2479-2484
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• 2018

The filter bank multicarrier modulation (FBMC) technique is one of multicarrier modulation technique (MCM), which is mainly used to improve channel capacity of cognitive radio (CR) network and frequency spectrum access technique. The existing FBMC System contains serial to parallel converter, normal QAM modulation, Radix2 inverse FFT, parallel to serial converter and poly phase filter. It needs high area, delay and power consumption. To further reduce the area, delay and power of FBMC structure, a new clock gating technique is applied in the QAM modulation, radix2 multipath delay commutator (R2MDC) based inverse FFT and unified addition and subtraction (UAS) based FIR filter with parallel asynchronous self time adder (PASTA). The clock gating technique is mainly used to reduce the unwanted clock switching activity. The clock gating is nothing but clock signal of flip-flops is controlled by gate (i.e.) AND gate. Hence speed is high and power consumption is low. The comparison between existing QAM and proposed QAM with clock gating technique is carried out to analyze the results. Conversely, the proposed inverse R2MDC FFT with clock gating technique is compared with the existing radix2 inverse FFT. Also the comparison between existing poly phase filter and proposed UAS based FIR filter with PASTA adder is carried out to analyze the performance, area and power consumption individually. The proposed FBMC with clock gating technique offers low power and high speed than the existing FBMC structures.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.1-8
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• 2004

A novol clock distribution scheme is proposed for high-speed and low-power digital system to minimize clock skew and reduce dynamic power consumption. This scheme has ideal zero-skew characteristic by using folded clock lines (FCL) and phase blending circuit. For analyzing suitable line structures to FCLs, microstrip line and coplanar line are placed with folded clock lines. Simulation results show that the maximum clock-skew between two receivers located 10mm apart is less than lops at 1㎓ and the maximum clock-skew between two receivers located 20mm apart is less than 60ps at 1㎓. Also the results show that the minimum skews of clock signals regardless of process, voltage, and temperature variation are invariant.

• Publications of The Korean Astronomical Society
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• v.22 no.4
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• pp.189-199
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• 2007

In this paper, we describe the proposed KVN (Korean VLBI Network) clock system in order to make the observation of the VLBI effectively. In general, the GPS system is widely used for the time information in the single dish observation. In the case of VLBI observation, a very high precise frequency standard is needed to perform the observation in accordance with the observation frequency using the radio telescope with over 100km distance. The objective of the high precise clock system is to insert the time-tagging information to the observed data and to synchronize it with the same clock in overall equipments which used in station. The AHM (Active Hydrogen Maser) and clock system are basically used as a frequency standard equipments at VLBI station. This system is also adopted in KVN. The proposed KVN clock system at each station consists of the AHM, GPS time comparator, standard clock system, time distributor, and frequency standard distributor. The basic experiments were performed to check the AHM system specification and to verify the effectiveness of implemented KVN clock system. In this paper, we briefly introduce the KVN clock system configuration and experimental results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.10
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• pp.1537-1544
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• 2022

When designing chip, it considers design specification, timing problem, and clock synchronization on place & route (P&R) process. P&R process is complicated because of considering various factors. Chip uses clock tree synthesis (CTS) to reduce clock path delay. The purpose of this study is to examine shallow-CTS algorithm for checking clock tree synthesizable. Using open source Parser-Verilog, register transfer level (RTL) synthesizable Verilog file is parsed and it uses Pre-CTS and Post-CTS process that is included shallow-CTS. Based on longest clock path in the Pre-CTS and Post-CTS stages, the standard deviation before and after buffer insertion is compared and analyzed for the accuracy of CTS. In this paper, It is expected that the cost and time problem could be reduced by providing a pre-clock tree synthesis verification method at the RTL level without confirming the CTS result using the time-consuming licensed EDA tool.

• Journal of Life Science
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• v.33 no.9
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• pp.730-735
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• 2023

In the past decade, numerous studies have been carried out to quantify aging with the help of artificial intelligence. Using DNA methylation data, various models have been developed; these are commonly called epigenetic clocks. Epigenetic age acceleration is usually associated with disease conditions. Schizophrenia is a mental illness associated with severe mental and physical stress. This disease leads to high mortality and morbidity rates in young people compared with other psychological disorders. In the past, the research community considered this disease to be related to the accelerated aging hypothesis. In the current study, we wanted to investigate the epigenetic age acceleration changes in schizophrenia patients to obtain epigenetic insights into the disease. To measure the epigenetic age acceleration, we used two different DNA methylation clock models, namely, Horvath clock and Epi clock, as these are pan-tissue models. We utilized 450k array data compatible with both clocks. We found a slower epigenetic acceleration in the patients' samples when we used the Epi clock. We further analyzed the differentially methylated CpG sites between the control and cases and performed pathway enrichment analysis. We found that most of the CpGs are involved in neuronal processes.