• 제어로봇시스템학회:학술대회논문집
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• 1999.10a
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• pp.281-283
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• 1999

This topic presents an inductor short turn testing. From the rudimentary principles, the quality factor(Q) decreases due to inductor short turn. Frequency response varies because of the variation of circuit inductance and resistance. In general, short turn circuit testing is performed by comparing the ratio of an inductance and resistance of inductor in that particular circuit. An alternative method can be done by considering the response of second order circuit which can give both dynamic and static testing, whereas static testing give an error results not more than 2 turns. For dynamic testing, the result is more accurate, which can test fur the short turn number form 1 turn onward.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.811-814
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• 1998

REcent research about current testing($\textrm{I}_{DDQ}$ testing) has been emphasizing that $\textrm{I}_{DDQ}$ testing in addition to the logical voltage testing is necessary to increase the fault coverage. The $\textrm{I}_{DDQ}$. testing can detect physical faults other than the classical stuck-at type fault, which affect reliability. One of the most critical issues in the $\textrm{I}_{DDQ}$ testing is to insert a built-in current sensor (BICS) that can detect abnormal static currents from the power supply or to the ground. This paper presents a new BICS for internal current testing for large CMOS logic circuits. The proposed BICS uses a single phase clock to minimize the hardware overhead. It detects faulty current flowing and converts it into a corresponding logic voltage level to make converts it into a corresponding logic voltage level to make it possible to use the conventional voltage testing techniqeus. By using current mirroring technique, the proposed BICS can work at very high speed. Because the proposed BICS almost does not affects normal operation of CUT(circuit under test), it can be used to a very large circuit without circuit partitioning. By altenating the operational modes, a circuit can be $\textrm{I}_{DDQ}$-tested as a kind of self-testing fashion by using the proposed BICS.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.5
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• pp.431-438
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• 2005

In this paper, we propose the built-in current testing circuit for improving reliability As the integrated CMOS circuits in a chip are increased, the testability on design and fabrication should be considered to reduce the cost of testing and to guarantee the reliability In addition, the high degree of integration makes more failures which are different from conventional static failures and introduced by the short between transistor nodes and the bridging fault. The proposed built-in current testing method is useful for detecting not only these failures but also low current level failures and faster than conventional method. In normal mode, the detecting circuit is turned off to eliminate the degradation of CUT(Circuits Under Testing). The differential input stage in detecting circuit prevents the degradation of CUT in test mode. It is expected that this circuit improves the quality of semiconductor products, the reliability and the testability.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.9
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• pp.1566-1570
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• 2007

[ $SF_6$ ] gas circuit breakers are widely used for short circuit current interruption in EHV(Extra High Voltage) or UHV(Ultra High Voltage) power systems. To develop $SF_6$ gas circuit breakers, the arc resistance value is necessary to compare experimental results to numerical ones. The arc resistance value can be obtained from a breaking test with a $SF_6$ gas circuit breaker. The direct testing or synthetic testing facility is widely used to verify the breaking ability for $SF_6$ gas circuit breakers. We employed the simplified synthetic testing facility to test a $SF_6$ gas circuit breaker prototype. The arc resistance characteristic was measured and calculated under the various experimental conditions. This arc resistance value can be used for verifying the numerical results from arc simulation in a circuit breakers.

• Journal of Electrical Engineering and Technology
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• v.7 no.5
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• pp.778-783
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• 2012

The synthetic short-circuit making test to adequately stress the circuit breaker has been specified as the mandatory test duty in the IEC 62271-100. The purpose of this test is to give the maximum pre-arcing energy during making operation. And this requires the making operation with symmetrical short-circuit current that is established when the breakdown between contact gap occurs near the crest of the applied voltage. Also, if the interrupting chamber of circuit breakers is designed as the type of common enclosure or the operation is made by the gang operated mechanism that three-phase contacts are operated by one common mechanism, three-phase synthetic making test is basically required. Therefore, several testing laboratories have developed and proposed their own test circuits to properly evaluate the breaker performance. With these technical backgrounds, we have developed the new alternative three-phase making circuit.

• Proceedings of the KIEE Conference
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• 1995.07b
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• pp.623-627
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• 1995

This paper describes analysis and optimization of Weil-Dobke synthetic testing circuit parameters, which is efficient and economical test method in high capacity AC circuit breaker. In this paper, analysis of synthetic short-circuit test circuit parameter proposed nondimensional factor that is reciprocal comparison value of circuit parameter and is not related to rated of circuit breaker, in particular, this study induce minimization of required energy of critical TRV generation specified in IEC 56 standards and present optimal design of synthetic short circuit testing facilities.

• The Journal of the Acoustical Society of Korea
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• v.18 no.3
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• pp.43-48
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• 1999

IDDQ testing is one of current testing methodologies which increases circuit's reliability by means of finding defects which can't be detected by functional testing in CMOS circuits. In this paper, we design a Built-In Current Sensor(BICS) circuit, which can be embedded in chip under test, that performs IDDQ testing. Furthermore, it is designed for IDDQ testing of memories and implemented to carry out testing at high-speed by using small number of transistors.

• Proceedings of the KIEE Conference
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• 2005.07a
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• pp.700-702
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• 2005

The most electrical apparatus should be able to withstand short-time current and peak current during a specified short time until circuit breakers have interrupted fault current. It defines the short-time withstand ability of electric a apparatus to be remain for a time interval under high fault current conditions. It is specified by both dynamic ability and thermal capability. KERI(Korea Electrotechlology Research Institute) recently constructed the new short-time current and low voltage short circuit testing facilities. This paper shows short- circuit calculation of transformer and describes high current measuring system, and evaluate the result of short-time withstand test used in $3{\phi}$ 90MVA short-time current testing facilities.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.49-63
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• 1997

This paper presents a current sensor that detects defects in CMOS integrated circuits using the current testing technique. The current sensor is built in a CMOS integrated circuit to test an abnormal current. The proposed circuit has a very small impact on the performance of the circuit under test during the normal mode. In the testing mode, the proposed circuit detects the abnormal current caused by permanent manufacturing defects and determines whether the circuit under test is defect-free or not. The proposed current sensor is simple and requires no external voltage and current sources. Hence, the circuit has less area and performance degradation, and is more efficient than any previous works. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects.

• Journal of the Korea Society of Computer and Information
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• v.6 no.1
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• pp.7-13
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• 2001

As the density of VLSI increases, the conventional logic testing is not sufficient to completely detect the new faults generated in design and fabrication processing. Recently. IDDQ testing becomes very attractive since it can overcome the limitations of logic testing. This paper presents a new BIC for the internal current test in CMOS logic circuit. Our circuit is composed of Magnetoresistive current sensor, level shifter, comparator, reference voltage circuit and a circuit be IDDQ tested as a kind of self-testing fashion by using the proposed BIC.