• Journal of information and communication convergence engineering
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• v.7 no.4
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• pp.453-458
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• 2009

This paper presents two methods of designing a Broadband Impedance Matching (BIM) circuit for maximizing a power line communication (PLC) equipment (or Modem) signal injection into its load at any power line connection port. This optimal (BIM) circuit design is achieved in two phases: Butterworth gain function and Tchebycheff gain function. According to the comparison of simulation and practical results, the performances of two gain functions on BIM are discussed.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.99.2-99
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• 2001

An electronically tunable current-mode second-order multifunctional filter is described in this paper. The proposed filter consists of two four-terminal floating nullors (FTFNs), two dual-output OTAs and two grounded capacitors. The circuit can simultaneously realize the lowpass, bandpass and highpass current transfer functions from the same configuration without changing the circuit configuration and elements. The natural angular frequency we and the parameter wo/Q can be orthogonally controlled through adjusting the transconductance gain of OTA. PSPICE simulation results are employed to confirm the circuit performance.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.80.1-80
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• 2002

In this article, an alternative analog multiplier circuit, using the translinear second-generation current conveyors with the external resistors. The realization method makes use of the inherited translinear loop of the current conveyor offering the positive-supply current that provides in the quartersquare algebraic identity. The proposed circuit operates in voltage mode and it achieves a high accuracy. The PSPICE simulation results confirm that the performances of the proposed multiplier circuit, such as dynamic range and accuracy, are agreed with the theoretical results.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.763-766
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• 2002

This paper proposes design of new linear bipolar OTAs composed of an hyperbolic function circuit and a triple-tail cell. Two types of the OTAs are presented; one employs a hyperbolic sine circuit and the other contains a hyperbolic cosine circuit. The linear input voltage ranges of the proposed OTAs are wider than that of the conventional triple-tail cell, though the power dissipation is smaller. The results of SPICE simulation show that satisfactory characteristics are obtained.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1041-1044
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• 2003

In this paper, a new CMOS fully integrated frequency-to-digital converter is proposed. The operation of the proposed circuit is based on a pulse-shrinking delay element. In the proposed circuit, a resolution of the converted digital output can be easily improved by increasing the number of the pulse-shrinking element. Also the input frequency range can be easily changed through controlling bias voltage in the pulse-shrinking element. The simulation of the designed circuit carried out by HSPICE using the CMOS 0.35${\mu}{\textrm}{m}$ process technology.

• ETRI Journal
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• v.8 no.1
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• pp.44-52
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• 1986

The main features of HILO-3 logic simulator are introduced. It is regarded as one of the most powerful logic simulator available now in electronic industry. The major functions and concepts are reviewed with some examples; circuit description using HDL (Hardware Description Language), waveform description using WDL (Waveform Description Language) and fault-free simulation for static RAM circuit. This program is expected to help the system designers, integrated circuit designers and test engineers.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.133-136
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• 2001

A new package design method to reduce resonance effect due to an IC package is represented. Frequency-variant circuit model of the power/ground plane was developed to accurately reflect the resonance. The circuit model is benchmarked with a full wave simulation, thereby verifying its accuracy. Then it was shown that the proposed technique can efficiently reduce the resonance due to the IC package.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.723-728
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• 1999

In this paper, we designed a Circular Path Built-In Self Test circuit and embedded it into a simple 8-bit microprocessor. Register cells of the microprocessor have been modified into Circular Path register cells and each register cells have been connected to form a scan chain. A BIST controller has been designed for controlling BIST operations and its operation has been verified through simulation. The BIST circuit described in this paper has increased size overhead of the microprocessor by 29.8% and delay time in the longest delay path from clock input to output by 2.9㎱.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.757-760
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• 1999

Depending upon the existence of the battery, transponder is divided into active and passive transponder. The passive transponder operates without battery and so has no limitation in its operating range and life time. But it needs the RF-DC conversion circuit. In this paper, the analysis and design of the RF-DC conversion circuit in passive transponder operated in high frequency is presented and is confirmed by simulation and experiment.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.975-978
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• 1999

The transmission line effects of IC interconnects have a substantial effect on a hish-speed VLSI circuit performance. The effective transmission lime parameters are changed with the increase of the operation frequency because of the skin of the skin effect, proximity effect, and silicon substrate. A new signal delay estimation methodology based on the RLC-distributed circuit model is presented ［2］. The methodology is demonstrated by using SPICE simulation and a high-frequency experiment technique.