• Progress in Superconductivity and Cryogenics
• /
• v.18 no.4
• /
• pp.30-34
• /
• 2016

In this study, a SFCL-combined DC circuit breaker system was proposed by applying the current-limiting technology for DC circuit breaking. The SFCL-combined circuit breaker system consists of a mechanical DC circuit breaker combined with superconductors. To ensure the reliable structure and operation of the SFCL-combined circuit breaker system, a simulation grid was designed using the EMTDC/PSCAD program, and simulation was conducted. The results showed that the SFCL-combined DC circuit breaker system with superconductors limited the maximum fault current by 37%. In addition, the burden on the DC circuit breaker was decreased by 87%.

• Journal of Sensor Science and Technology
• /
• v.10 no.2
• /
• pp.142-147
• /
• 2001

Using transmission-line equivalent circuit based on cross-field model for an interdigital acoustic wave transducer, an efficient simulation technique of SAW filters by SPICE is proposed. Propagation of surface acoustic wave is modeled as transmission line so that frequency-dependent circuit elements are not needed in the equivalent circuit of an interdigital transducer. Because the equivalent circuits for frequency-dependent circuit elements are not derived approximately, and a small number of circuit elements are used in the equivalent circuit for filters, simulation time is much reduced. The utility of the proposed technique is demonstrated through simulation for the characteristics of SAW filters such as insertion loss, input admittance, passband ripple, and harmonic frequency response.

• Journal of the Korea Society for Simulation
• /
• v.3 no.1
• /
• pp.107-114
• /
• 1994

This paper describes an integrated environment for logic circuit simultion which is an important step of logic circuit design. The system consists of a logic simulator kernel, an expandible element routine library. a functional level element routine generator, several HDL input parsers, and a postprocessor. The system can simulate the same system in several levels of hierarchy. The experimental result shows that the system is very efficient and useful for design of logic circuits.

• Journal of the Semiconductor & Display Technology
• /
• v.6 no.2 s.19
• /
• pp.49-52
• /
• 2007

Characteristics of an active pixel switch readout circuit were studied by SPICE simulation. A simple readout circuit consists of an operation amplifier, a diode, and a down-counter was suggested, and its successful operation was verified by showing that the differences in the detected signal intensity are accordingly converted to modulation of the voltage pulses generated by the comparator. A scheme to use these pulses to generate the original image was also put forward.

• Proceedings of the KIEE Conference
• /
• 2007.07a
• /
• pp.874-875
• /
• 2007

This paper introduces major potential faults of IPMSM and their simulation realization methods. The faults of IPMSM, generally, contain single-phase open circuit, single-phase or 3-phase short circuit, and uncontrolled generation. When different fault occurs, the circuit of total system including motor and inverter also will be changed. Therefore, it is necessary to analyze and establish independent model for each kind of fault. In this paper, first, the drive circuit is analyzed as different fault type. Then, the corresponding simulation results solved in Simulink@MATLAB are given. The absence of experiment results leads that the veracity of simulation results can not be verified, but the tendency will be explained by theory analysis.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.16 no.5
• /
• pp.627-634
• /
• 2006

We have proposed the methods how to control the slope of CMOS inverter's characteristic and how to shift it in y axis. We control the MOS transistor threshold voltage for these methods. By observing that two transistors are in saturation region at the center of the CMOS inverter's characteristic, we have presented how to make the characteristic for one pole neuron. The circuit level simulation is used for verifying the proposed method. PSpice(OrCAD Co.) is used for circuit level simulation.

• 제어로봇시스템학회:학술대회논문집
• /
• 2005.06a
• /
• pp.792-793
• /
• 2005

Circuit testing process is very important in IC Manufacturing there are two ways in research for circuit testing improvement. These are ATPG Tool Design and Test simulation application. We are interested in how to use parallel technique such as one-side communication, parallel IO and dynamic Process with data partition for circuit testing improvement and we use one-side communication technique in this paper. The parallel ATPG Tool can reduce the test pattern sets of the circuit that is designed in laboratory for make sure that the fault is not occur. After that, we use result for parallel circuit test simulation to find fault between designed circuit and tested circuit. From the experiment, We use less execution time than non-parallel Process. And we can set more parameter for less test size. Previous experiment we can't do it because some parameter will affect much waste time. But in the research, if we use the best ATPG Tool can optimize to least test sets and parallel circuit testing application will not work. Because there are too little test set for circuit testing application. In this paper we use a standard sequential circuit of ISCAS89.

• 한국정보통신설비학회:학술대회논문집
• /
• 2007.08a
• /
• pp.27-30
• /
• 2007

This paper deals with an equivalent circuit model for RF passive components. Rational functions are obtained from the frequency responses of EM simulation by using Foster canonical partial fraction expressions. The Vector Fitting(VF) and the Adaptive Frequency Sampling(AFS) scheme are also implemented to obtain the rational functions. A passivity enforcement algorithm is applied to ensure the stability of the equivalent circuit model. In order to verify the schemes, S parameters of the equivalent circuit model is compared to those of EM simulation in case of the microstrip line structure with 3 slots in ground.

• Journal of information and communication convergence engineering
• /
• v.6 no.3
• /
• pp.275-278
• /
• 2008

In this paper, I propose the full CMOS FLL(frequency locked loop) circuit. The proposed FLL circuit has a simple structure which contains a FVC(frequency-to-voltage converter), an operational amplifier and a VCO(voltage controlled oscillator). The operation of FLL circuit is based on frequency comparison by the two FVC circuit blocks. The locking time of FLL is short compared to PLL(phase locked loop) circuit because the output signal of FLL is synchronized only in frequency. The circuit is designed by 0.35${\mu}m$ process and simulation carried out with HSPICE. Simulation results are shown to illustrate the performance of the proposed FLL circuit.

• 제어로봇시스템학회:학술대회논문집
• /
• 2005.06a
• /
• pp.1192-1195
• /
• 2005

This paper presents the realization of a multiple-input maximum circuit, which is operated in a current-mode. The proposed circuit operates with bi-directional input current signal and employs 5n+4 transistors for n inputs. The realization method is suitable for fabrication using CMOS technology. The proposed circuit is useful building block for the real-time systems. The performances of the proposed bi-directional maximum circuit were studied using the PSPICE analog simulation program. The simulation results verified the circuit performances are agreed with the expected values.