• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1627-1634
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• 2021

This paper introduces a low-power compact ADC circuit for analog Convolutional filter for low-power neural network accelerator SOC. While convolutional neural network accelerators can speed up the learning and inference process, they have drawback of consuming excessive power and occupying large chip area due to large number of multiply-and-accumulate operators when implemented in complex digital circuits. To overcome these drawbacks, we implemented an analog convolutional filter that consists of an analog multiply-and-accumulate arithmetic circuit along with an ADC. This paper is focused on the design optimization of a low-power 8bit SAR ADC for the analog convolutional filter accelerator We demonstrate how to minimize the capacitor-array DAC, an important component of SAR ADC, which is three times smaller than the conventional circuit. The proposed ADC has been fabricated in CMOS 65nm process. It achieves an overall size of 1355.7㎛², power consumption of 2.6㎼ at a frequency of 100MHz, SNDR of 44.19 dB, and ENOB of 7.04bit.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.93-96
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• 2008

This paper describes an efficient design of a multi-standard Viterbi decoder that supports multiple constraint lengths and code rates. The Viterbi decode. is parameterized for the code rates 1/2, 1/3 and constraint lengths 7, 9, thus it has four operation modes. In order to achieve low hardware complexity and low power, an efficient architecture based on hardware sharing techniques is devised. Also, the optimization of ACCS (Accumulate-Subtract) circuit for the one-point trace-back algorithm reduces its area by about 35% compared to the full parallel ACCS circuit. The parameterized Viterbi decoder core has 79,818 gates and 25,600 bits memory, and the estimated throughput is about 105 Mbps at 70 MHz clock frequency.

• Journal of Hydrogen and New Energy
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• v.22 no.3
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• pp.292-298
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• 2011

This study examines the effects of the ambient temperature (AT), methanol feeding temperature (MFT), methanol concentration (MC) and methanol flow rate (MFR) on the performance and cell temperature (CT) of a 5-stacked direct methanol fuel cell (DMFC). The AT, MFT, MC, and MFR are varied from $-10^{\circ}C$ to $+40^{\circ}C$, $50^{\circ}C$ to $90^{\circ}C$, 0.5M to 3.0M and 11.7 mL $min^{-1}$ to 46.8 mL $min^{-1}$, respectively. The performance of the DMFC under various operating conditions is analyzed from the I-V polarization curve, and the methanol crossover is estimated by gas chromatography (GC). The performance of the DMFC improves significantly with increasing AT. The open circuit voltage (OCV) decreases with increasing MC due to the enhanced likelihood of methanol crossover. The cell performance is improved significantly when the MFR is increased from 11.7 mL $min^{-1}$ to 28.08 mL $min^{-1}$. The change in cell performance is marginal with further increases in MFR. The CT increases significantly with increasing AT. The effect of the MFT and MFR is moderate, and the effect of MC is marginal on the CT of the DMFC.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.152-152
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• 2016

We studied the effect of the silver grid size on graphene transparent conducting films for flexible organic solar cells (OSCs). The silver grid was used an assistant layer of the graphene to reduce the sheet resistance of substrates. Silver grid with various graphene sizes for optimizing transmittance and sheet resistance of substrates were fabricated on polyethylene terephthalate (PET) substrates to form the hybrid films. The optimized grid geometry on the single layer graphene (SLG) was the grid dimension $200{\mu}m{\times}200{\mu}m{\times}50nm{\times}2{\mu}m$ (length ${\times}$ width ${\times}$ height ${\times}$ linewidth), where the sheet resistance was $55.73{\Omega}/square$ with the average transmittance of ~ 92.83 % at 550 nm. The properties of the OSCs fabricated using SLG with optimized silver grids on PET substrates show a short circuit current of $10.9mA/cm^2$, an open circuit voltage of 0.58 V, a fill factor of 60.8 %, and a power conversion efficiency (PCE) of 3.9 %. The PCE was improved about 91% than that of the OSCs using the SLG without the silver grid. These results demonstrate that the optimized grid geometry to the based on the graphene transparent electrodes contribute to improving the performance of OSCs.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.8
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• pp.1163-1171
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• 2017

The problem of fault current to exceed the rated capacity of a power circuit breaker can cause a serious accident to hurt the reliability of the power system. In order to solve this issue, current limiting reactors and circuit breakers with increased capacity are utilized but these solutions have some technical limitations. Back-to-back high voltage direct current(BTB HVDC) may be applied for reducing the fault current. When BTB HVDCs are installed for reduction in fault current, selecting the optimal location of the BTB HVDC without causing overload of line power becomes a key point. In this paper, we use genetic algorithm to find optimal location effectively in a short time. We propose a new methodology for determining the BTB HVDC optimal location to reduce fault current without causing overload of line power in metropolitan areas. Also, the procedure of performing the calculation of fault current and line power flow by PSS/E is carried out automatically using Python. It is shown that this optimization methodology can be applied effectively for determining the BTB HVDC optimal location to reduce fault current without causing overload of line power by a case study.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.9
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• pp.47-53
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• 2011

The signal transmission properties of the connector such as insertion loss and return loss are investigated using analysis procedure of S-parameter simulation, equivalent model extraction, and characteristic impedance calculation. S-parameter simulation is performed by connector's modeling and solving based on 3-dimensional finite element method. The connector's equivalent model of ${\pi}$ type is are proposed and extracted with an optimization process of circuit analysis simulator. The characteristic impedance of the connector is calculated with results of circuit analysis simulation and S-parameter data. According to the connector's characteristic impedance, it's revised design is carried out. In this work, the connector's effective contact area is increased and its body is applied as a high dielectric material in order to increase its capacitance and then obtain impedance matching. Therefore, return loss of the connector is improved by approximately 10 dB due to its design revision.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.11-15
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• 2010

In this paper, we focused on the optimization of bonding conditions for the successful thermo-compression bonding of electrodes between the RPCB and FPCB with Sn-Pb solder. The peel strength was proportionally affected by the bonding conditions, such as pressure, temperature, and time. In order to figure out an optimized bonding condition, fracture energies were calculated through F-x (force-displacement) curves in the peel test. The optimum condition for the thermo-compression bonding of electrodes between the RPCB and FPCB was found to be temperature of $225^{\circ}C$ and time of 7 s, and its peel strength was 22 N/cm.

• Journal of international Conference on Electrical Machines and Systems
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• v.3 no.3
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• pp.272-275
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• 2014

An improved fuzzy Kalman filtering speed estimation scheme was proposed by means of measuring stator side voltage and current value based on vector control state equation of induction motor. The designed fuzzy adaptive controller conducted recursive online correction of measurement noise covariance matrix by monitoring the ratio of theory residuals and actual residuals to make it approach real noise level gradually, allowing the filter to perform optimal estimation to improve estimation accuracy of EKF. Meanwhile, co-simulation scheme based on MATLAB and Ansoft was proposed in order to improve simulation accuracy. Field-circuit coupling problems of induction motor under the action of vector control were solved and the parameter optimization accuracy was improved dramatically. The simulation and experimental results show that this algorithm has a strong ability to inhibit the random measurement noise. It is able to estimate motor speed accurately, and has superior static and dynamic characteristics.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.7
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• pp.50-57
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• 2000

We propose a logic synthesis algorithm for the design of FPGAs operating at high speed. FPGA is a novel technology that provides programmability in the field. Because of short turnaround time and low manufacturing cost, FPGA has been noticed as an ideal device for system prototyping. Despite these merits, FPGA has drawbacks, namely low integration and long delay time comparing to ASIC. The proposed algorithm partitions a given circuit into subcircuits utilizing a kernel divisor such that the subcircuits can be performed at the same time, hence reducing the delay of the circuit. Experimental results on the MCNC benchmark show that the proposed algorithm is effective by generating circuits having 19.1% les delay on average, when compared to the FlowMap algorithm.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.72-79
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• 2003

Classical designs of optical transimpedance preamplifier for p-i-n photodiode receiver circuits generally employ common source transimpedance input stages. In this paper, we explore the design of a class of current-mode optical transimpedance preamplifier based upon common gate input stages. A feature of current-mode optical transimpedance preamplifier is high gain and high bandwidth. The bandwidth of the transimpedance preamplifier can also be increased by the capacitive peaking technique. In this paper we included the development and application of a circuit analysis technique based on the minimum noise. We develop a general formulation of the technique, illustrate its use on a number of circuit examples, and apply it to the design and optimization of the low-noise transimpedance amplifier. Using the noise minimization method and the capacitive peaking technique we designed a transimpedance preamplifier with low noise, high-speed current-mode transimpedance preamplifier with a 1.57GHz bandwidth, and a 2.34K transimpedance gain, a 470nA input noise current. The proposed preamplifier consumes 16.84mW from a 3.3V power supply.