• Tunnel and Underground Space
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• v.32 no.6
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• pp.345-352
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• 2022

The existing NATM (New Austrian Tunneling Method) has induced civil compliants due to blasting vibration and noise. Machanized excavation methods such as TBM (Tunnel Boring Machine) are being adopted in the planning and construction of tunneling projects. Shield TBM method is composed of repetition processes of TBM excavation and segment installation, the machine has to be stopped during the later process. Consecutive excavation technology using helical segment is under developing to minimize the stoppage time. The modification of thrust jacks and module are planned to ensure the advance force acting on the inclined surface of helical segment. Also, the integrated system design of hydraulic circuit will be remodeled. This means that the system deactivate the jacks on the installing segment while the others automatically act the thrusting forces on the existing segments. This report briefly introduces the mechanical research part of the current consecutive excavation technological development project of TBM.

• Journal of Advanced Information Technology and Convergence
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• v.10 no.1
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• pp.71-83
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• 2020

In this paper, we propose a system that can detect the shape of a hand at high speed using an FPGA. The hand-shape detection system is designed using Verilog HDL, a hardware language that can process in parallel instead of sequentially running C++ because real-time processing is important. There are several methods for hand gesture recognition, but the image processing method is used. Since the human eye is sensitive to brightness, the YCbCr color model was selected among various color expression methods to obtain a result that is less affected by lighting. For the CbCr elements, only the components corresponding to the skin color are filtered out from the input image by utilizing the restriction conditions. In order to increase the speed of object recognition, a median filter that removes noise present in the input image is used, and this filter is designed to allow comparison of values and extraction of intermediate values at the same time to reduce the amount of computation. For parallel processing, it is designed to locate the centerline of the hand during scanning and sorting the stored data. The line with the highest count is selected as the center line of the hand, and the size of the hand is determined based on the count, and the hand and arm parts are separated. The designed hardware circuit satisfied the target operating frequency and the number of gates.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.1
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• pp.33-39
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• 2022

A multi-phase brushless direct current (BLDC) motor is widely used in large-capacity electric propulsion systems such as submarines and electric ships. In particular, in the field of military submarines, the polyphaser motor must suppress torque ripple in various failure situations to reduce noise and ensure stable operation for a long time. In this paper, we propose a polyphaser current control method that can improve efficiency and reduce torque ripple by minimizing the increase in stator winding loss at maximum output torque by controlling the phase angle and amplitude of the steady-state current during open circuit failure of the stator winding. The proposed control method controls the magnitude and phase angle of the healthy phase current, excluding the faulty phase, to compensate for the torque ripple that occurs in the case of a phase open failure of the motor. The magnitude and phase angle of the controlled steady-state current are calculated for each phase so that copper loss increase is minimized. The proposed control method was verified using hardware-in-the-loop simulation (HILS) of a 12-phase BLDC motor. HILS verification confirmed that the increase in the loss of the stator winding and the magnitude of the torque ripple decreased compared with the open phase fault of the motor.

• Journal of the Korea Institute of Military Science and Technology
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• v.26 no.3
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• pp.227-233
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• 2023

In this paper, to substitute the existing TWTA(Travailing Wave Tube Amplifier) component in small radar system, we developed the Ku band SSPA(Solid-State Power Amplifier) based on the fabrication of power MMIC (Monolithic Microwave Integrated Circuit) chips. For the development of the 500 W SSPA, the 40 W-grade power MMIC was designed by ADS(Advanced Design System) at Keysight company with UMS GH015 library, and was processed by UMS foundry service. And 70 W main power modules were achieved the 2-way T-junction combiner method by using the 40 W-grade power MMICs. Finally, the 500 W SSPA was fabricated by the wave guide type power divider between the drive power amplifier and power modules, and power combiner with same type between power modules and output port. The electrical properties of this SSPA had 504 W output power, -58.11 dBc spurious, 1.74 °/us phase variation, and -143 dBm/Hz noise level.

• Journal of IKEEE
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• v.28 no.2
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• pp.174-179
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• 2024

In this work, we introduce a complementary metal-oxide semiconductor(CMOS)-based integrated circuit(IC) measurement set-up for quantum computer control and read-out using a cryogenic refrigerator. CMOS circuits have to operate at extremely low temperatures of 3 to 5 K for qubit stability and noise reduction. The existing cryogenic measurement system is liquid helium quenching, which is expensive due to the long-term use of expendable resources. Therefore, we describe a cryogenic measurement system based on a closed cycle refrigerator (CCR) that is cost-free even when using helium gas for long periods of time. The refrigerator capable of reaching 4.7 K was built using a Gifford-Mcmahon(G-M) type cryocooler. This is expected to be a cryogenic refrigerator set-up with excellent price competitiveness.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.23 no.8
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• pp.759-769
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• 2013

Electronic equipment has been applied to virtually every area associated with commercial, industrial, and military applications. Specifically, electronics have been incorporated into avionics components installed in aircraft. This equipment is exposed to dynamic loads such as vibration, shock, and acceleration. Especially, avionics components installed in a helicopter are subjected to simultaneous sine and random base excitations. These are denoted as sine on random vibrations according to MIL-STD-810F, Method 514.5. In the past, isolators have been applied to avionics components to reduce vibration and shock. However, an isolator applied to an avionics component installed in a helicopter can amplify the vibration magnitude, and damage the chassis, circuit card assembly, and the isolator itself via resonance at low-frequency sinusoidal vibrations. The objective of this study is to investigate the dynamic characteristics of an avionics component installed in a helicopter and the structural dynamic modification of its tray plate without an isolator using both a finite element analysis and experiments. The structure is optimized by dynamic loads that are selected by comparing the vibration, shock, and acceleration loads using vibration and shock response spectra. A finite element model(FEM) was constructed using a simplified geometry and valid element types that reflect the dynamic characteristics. The FEM was verified by an experimental modal analysis. Design parameters were extracted and selected to modify the structural dynamics using topology optimization, and design of experiments(DOE). A prototype of a modified model was constructed and its feasibility was evaluated using an FEM and a performance test.

• Korean Journal of Optics and Photonics
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• v.24 no.1
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• pp.1-8
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• 2013

In this paper, we report design, fabrication and characterization of the WBRM (Wide Band Receiver Module) for LADAR (LAser Detection And Ranging) application. The WBRM has been designed and fabricated using self-made APD (Avalanche Photodiode) and TIA (Trans-impedance Amplifier). The APD and TIA chips have been integrated on 12-pin TO8 header using self-made ceramic submount and circuit. The WBRM module showed 450 ps of rise time, and corresponding 780 MHz bandwidth. Furthermore, it showed very low output noise less than 0.8 mV, and higher SNR than 15 for 150 nW of MDS(Minimum Detectable Signal). To the author's knowledge, this is the best performance of an optical receiver module for LIDAR fabricated by 200 um InGaAs APD.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.53-60
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• 2005

This work proposes a 10b 100 MS/s $1.4\;mm^2$ CMOS ADC for low-power multimedia applications. The proposed two-step pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The wide-band SHA employs a gate-bootstrapping circuit to handle both single-ended and differential inputs with 1.2 Vp-p at 10b accuracy while the second-stage flash ADC employs open-loop offset sampling techniques to achieve 6b resolution. A 3-D fully symmetrical layout reduces the capacitor and device mismatch of the first-stage MDAC. The low-noise references are integrated on chip with optional off-chip voltage references. The prototype 10b ADC implemented in a 0.18 um CMOS shows the maximum measured DNL and INL of 0.59 LSB and 0.77 LSB, respectively. The ADC demonstrates the SNDR of 54 dB, the SFDR of 62 dB, and the power dissipation of 56 mW at 100 MS/s.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.11
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• pp.51-62
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• 2003

This paper presents a novel survivor memeory management and decoding techniques with sequential backward state transition control in the trace back Viterbi decoder. The Viterbi algorithm is an maximum likelihood decoding scheme to estimate the likelihood of encoder state for channel error detection and correction. This scheme is applied to a broad range of digital communication such as intersymbol interference removing and channel equalization. In order to achieve the area-efficiency VLSI chip design with high throughput in the Viterbi decoder in which recursive operation is implied, more research is required to obtain a simple systematic parallel ACS architecture and surviver memory management. As a method of solution to the problem, this paper addresses a progressive decoding algorithm with sequential backward state transition control in the trace back Viterbi decoder. Compared to the conventional trace back decoding techniques, the required total memory can be greatly reduced in the proposed method. Furthermore, the proposed method can be implemented with a simple pipelined structure with systolic array type architecture. The implementation of the peripheral logic circuit for the control of memory access is not required, and memory access bandwidth can be reduced Therefore, the proposed method has characteristics of high area-efficiency and low power consumption with high throughput. Finally, the examples of decoding results for the received data with channel noise and application result are provided to evaluate the efficiency of the proposed method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.7-13
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• 2009

This paper presents a multi-channel transceiver that achieves a data rate of 3.125Gb/s/ch. The LVDS is used because of its noise immunity and low power consumption. And a pre-emphasis circuit is also proposed to increase the transmitter speed. On the receiver side, a low-power CDR(clock and data recovery) using 1/4-rate clock based on dual-interpolator is proposed. The CDR generates needed additional clocks in each recovery part internally using only inverters. Therefore each part can be supplied with the same number of 1/4-rate clocks from a clock generator as in 1/2-rate clock method. Thus, the reduction of a clock frequency relaxes the speed limitation and lowers power dissipation. The prototype chip is comprised of two channels and was fabricated in a $0.18{\mu}m$ standard CMOS process. The output jitter of transmitter is loops, peak-to-peak(0.31UI) and the measured recovered clock jitter is 47.33ps, peak-to-peak which is equivalent to 3.7% of a clock period. The area of the chip is $3.5mm^2$ and the power consumption is about 119mW/ch.