• ETRI Journal
• /
• v.29 no.3
• /
• pp.371-380
• /
• 2007

This paper proposes a new automatic compensation network (ACN) for a system-on-chip (SoC) transceiver. We built a 5 GHz low noise amplifier (LNA) with an on-chip ACN using 0.18 ${\mu}m$ SiGe technology. This network is extremely useful for today's radio frequency (RF) integrated circuit devices in a complete RF transceiver environment. The network comprises an RF design-for-testability (DFT) circuit, capacitor mirror banks, and a digital signal processor. The RF DFT circuit consists of a test amplifier and RF peak detectors. The RF DFT circuit helps the network to provide DC output voltages, which makes the compensation network automatic. The proposed technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance, gain, and noise figure using the developed mathematical equations. The ACN automatically adjusts the performance of the 5 GHz LNA with the processor in the SoC transceiver when the LNA goes out of the normal range of operation. The ACN compensates abnormal operation due to unusual thermal variation or unusual process variation. The ACN is simple, inexpensive and suitable for a complete RF transceiver environment.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.8
• /
• pp.1705-1712
• /
• 2004

This paper presents a new low-cost RF Built-In Self-Test (BIST) circuit for measuring transducer voltage gain, noise figure and input impedance of 5.25GHz low noise amplifier (LNA). The BIST circuit is designed using 0.18${\mu}{\textrm}{m}$ SiGe technology. The test technique utilizes input impedance matching and output transient voltage measurements. The technique is simple and inexpensive. Total chip size has additional area of about 18% for BIST circuit.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2004.05b
• /
• pp.635-641
• /
• 2004

This paper presents a new low-cost RF Built-In Self-Test (BIST) circuit for measuring transducer voltage gain, noise figure and input impedance of 5.25GHa low noise amplifier (LNA). The BIST circuit is designed using 0.18${\mu}{\textrm}{m}$ SiGe technology. The test technique utilizes input impedance matching and output transient voltage measurements. The technique is simple and inexpensive. Total chip size has additional area of about 18% for BIST circuit.

• Journal of Korea Society of Digital Industry and Information Management
• /
• v.19 no.2
• /
• pp.11-25
• /
• 2023

With the increasing advancement of VLSI technology, health care system is also developing to serve the humanity with better care. Therefore, biomedical implantable devices are one of the amazing important invention of scientist to collect data from the body cell for the diagnosis of diseases without any pain. This Biomedical implantable transceiver circuit has several important issues. Oscillator is one of them. For the design flexibility and complete transistor-based architecture ring oscillator is favorite to the oscillator circuit designer. This paper represents the design and analysis of the a 9-stage CMOS ring oscillator using cadence virtuoso tool in 180nm technology. It is also designed to generate the carrier signal of 403.5MHz frequency. Ring oscillator comprises of odd number of stages with a feedback circuit forming a closed loop. This circuit was designed with 9-stages of delay inverter and simulated for various parameters such as delay, phase noise or jitter and power consumption. The average power consumption for this oscillator is 9.32㎼ and average phase noise is only -86 dBc/Hz with the source voltage of 0.8827V.

• 제어로봇시스템학회:학술대회논문집
• /
• 1996.10b
• /
• pp.609-611
• /
• 1996

Zero-Cross Detector makes pilot signal to control the power to CEDM(Control Element Drive Mechanism). Existing Zero-Cross Detectors has had a problem which can cause unexpected reactor trip resulted from fluctuating frequency of input signal coming from M/G Set. The existing Zero-Cross Detector can't work properly when power frequency is varying because it was designed to work under stable M/G Set operation, and produces wrong pilot signal and output voltage. In this report the Zero-Cross Detector is improved to resolve voltage fluctuating problem by using new devices such as digital noise filtering circuit, variable cycle compensator and alarm circuit. And through the performance verification it shows that new circuit is better than old one. If suggested detector is applied to plant, it is possible to use it under House Load Operation because stable voltage can be generated by new Zero-Cross Detector.

• Transactions of the Korean Society for Noise and Vibration Engineering
• /
• v.14 no.6
• /
• pp.455-462
• /
• 2004

This paper is concerned with the implementation of the active vibration suppression controller using analog circuit and microprocessor. The target active vibration controller is the positive position feedback(PPF) controller since it provides a simple algorithm suitable for both analog circuit and digital controllers. In this study, the analog PPF controller is realized using an operational amplifier and the digital PPF controller is realized using a low-cost micro-controller. The circuit diagrams are explained in detail. We then discuss the advantages and disadvantages of both methods from the view of practical implementation. Experimental results show that both implementation methods can be effectively used for the active vibration control but need to be chosen based on the mission objective.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2007.08a
• /
• pp.822-824
• /
• 2007

This paper investigated a gate driver circuit with amorphous silicon for mobile TFT-LCD. In the conventional circuit, the fluctuation of the off-state voltage causes the fluctuation of gate line voltages in the panel and then image quality becomes worse. Newly designed gate driver circuit with dynamic switching inverter and carry out signal reduce the fluctuation of the off-state voltage because dynamic switching inverter is holding the off-state voltage and the delay of carry signal is reduced. The simulation results show that the proposed a-Si:H gate driver has low noise and high stability compared with the conventional one.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.12 no.1
• /
• pp.65-70
• /
• 2001

This paper presents a Receiver MMIC for the CDMA terminal. The complete circuit is composed of Low Noise Amplifier, Down Conversion Mixer, Intermediate Frequency Amplifier and Bias circuit. The Bias circuit implementation, which allows for compensation for threshold voltage and power supply voltage variation are provided. The proposed topology has high linearity and low noise characteristics. Results of the designed circuit are as follows: Overall conversion gain is 28.5 dB, input IP3 of LNA is 8 dBm, input IP3 of down conversion mixer is 0 dBm and total DC current consumption is 22.1 mA.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.13 no.2
• /
• pp.123-128
• /
• 2020

A low phase noise phase locked loop (PLL) with negative feedback loop including frequency variation sensing circuit (FVSC) has been proposed. The FVSC senses the frequency variation of voltage controlled oscillator output signal and controls the volume of electric charge in loop filter capacitance. As the output frequency of the phase locked loop increases, the FVSC reduces the loop filter capacitor charge. This causes the loop filter output voltage to decrease, resulting in a phase locked loop output frequency decrease. The added negative feedback loop improves the phase noise characteristics of the proposed phase locked loop. The size of capacitance used in FVSC is much smaller than that of loop filter capacitance resulting in no effect in the size of the proposed PLL. The proposed low phase noise PLL with FVSC is designed with a supply voltage of 1.8V in a 0.18㎛ CMOS process. Simulation results show the jitter of 273fs and the locking time of 1.5㎲.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.15 no.6
• /
• pp.590-598
• /
• 2004

An active capacitance circuit which employs series feedback network for the implement of negative resistance and low noise operation is analyzed in depth and its application to low noise active RF BPF's is discussed. Whereas many authors reported a lot of circuits that embody negative resistance circuit most of them have concerns for the equivalent resistance and reactance value at the center frequency. In this case, it could be possible to face a problem that the negative resistance circuit becomes unstable, or have poor flatness in passband because of insufficient forecast for the negative resistance values as the frequency goes higher or lower. In this paper, we extracted the exact equivalent values of this circuit and analyzed the RF characteristics with the varying the values of active devices and feedback circuits and presented the method that the flatness of passband can be improved. We have designed a 4-pole active BPF, which has the bandwidth of 60 ㎒, 0.67 ㏈ insertion loss, 0.3 ㏈ ripple, and noise figure of 3.0 ㏈ at 1.99 ㎓ band.