• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.108.6-108
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• 2001

The basic circuit block diagram of CMOS current mode sum and subtract circuit is present in this paper. The purpose circuit consists of the invert current circuit and the basic current mirror. The outputs of the circuit are the summing of the both input current [lx+ly] and also the subtract of the both input current [lx+(-ly)]. The SPICE simulation results of the electrical characteristics with level 7 (BSIM3 model version 3.1) MOSFET transistor model of the circuit such as the input dynamic range, the frequency response and some system application have been shown and analyzed.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.448-451
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• 2000

This paper proposed a snubber circuit for flying capacitor multilevel inverter and converter. The proposed snubber circuit makes use of Undeland snubber as basic snubber as basic snubber unit and has such an advantage of Undeland snubber used in the two-level inverter. Comparing conventional RCD/RLD snubber for multilevel in verter and converter the proposed snubber keeps such a good features as fewer number of components improved efficiency of system due to low loss snubber and reduction of voltage stress of main switching devices due to low overvoltage. Furthermore the proposed concept of constructing a snubber circuit for flying capacitor 3-level inverter and converter can apply to any level of them. In this paper the proposed snubber applies to three-level flying capacitor inverter and demonstrates its feature by computer simulation and experimental result.

• Journal of Electrical Engineering and Technology
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• v.6 no.2
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• pp.270-274
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• 2011

This paper presents a parameterized simulation program with integrated circuit emphasis (SPICE) model of a two-level microbolometer based on negative-temperature-coefficient thin films, such as vanadium oxide or amorphous silicon. The proposed modeling begins from the electric-thermal analogy and is realized on the SPICE modeling environment. The model consists of parametric components whose parameters are material properties and physical dimensions, and can be used for the fast design study, as well as for the co-design with the readout integrated circuit. The developed model was verified by comparing the obtained results with those from finite element method simulations for three design cases. The thermal conductance and the thermal capacity, key performance parameters of a microbolometer, showed the average difference of only 4.77% and 8.65%, respectively.

• Journal of IKEEE
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• v.28 no.2
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• pp.204-208
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• 2024

In this paper, we propose an ESD protection circuit that applies structural changes to LVTSCR, a general low-voltage ESD protection circuit, to improve the current driving capability (IEC-ESD) characteristics of the ESD protection circuit. Power consumption was minimized by separating the area where the electric field and ESD current path are formed in the LVTSCR structure, and the electrical characteristics were analyzed and current driving characteristics were improved. Structural problems resulting from deterioration of system level characteristics were analyzed through simulation, and the characteristics were verified by reflecting this. The electrical characteristics of the proposed ESD protection circuit were verified using a TCAD simulator and analyzed through HBM modeling and system level modeling. In addition, silicon production and HBM 10kV characteristics were verified through DB-Hitek 0.18um BCD process.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.4
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• pp.116-126
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• 1994

In this paper, the switch-level fault simulator for CMOS circuits with a gate-to-drain/source short fault is implemented. A fault model used in this paper is based on the graphical analysis of the electrical characteristics of the faulty MOS devices and the conversion of the faulty CMOS circuit to the equivalent faulty CMOS inverter in order to find its effect on the successive stage. This technique is very simple and has the increased accuracy of the simulation. The simulation result of the faulty circuit using the implemented fault simulator is compared with the result of the SPICE simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.3
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• pp.421-426
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• 2002

Hybrid cascade multilevel PWM inverter has advantages of hybrid structure which enhances the better utilization of power semiconductor switches, that is, both hi호 power-low frequency switch, GTO and low power-high frequency switch, IGBT can be used in the same circuit. In this paper, a static var compensator using hybrid cascade 5-level PWM inverter is presented for high voltage/high power applications. The proposed system is modelled by circuit DQ transformation, and thus an equivalent circuit is obtained which reveals the important characteristics of the system and lead to the related equations. Finally, circuit structure and characteristics is presented and the validity of the characteristics analysis is shown through PSIM simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.4
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• pp.292-299
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• 2010

With scaled technology, timing analysis of circuits becomes more and more difficult. In this paper, we review recently developed circuit simulation techniques created to deal with the cost issues of transistor-level simulations. Various techniques for fast SPICE simulations and Monte Carlo simulations are introduced. Moreover, process and aging variation issues are mentioned, along with promising methodologies.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.76-83
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• 2006

We proposed a new level shifter circuit architecture. The prposed circuit can provide high output voltage upto 15V by taking 3.3V logic signal compared to the conventional level shifter. The unposed circuit has compatible speed, low power consumption and chip size. We have confirmed the operation by conducting HSPICE simulation.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.408-409
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• 2011

본 논문에서는 전력전자 시스템 해석 시 PSpice와 Simulink를 이용한 Co-Simulation방법으로 회로 레벨(Circuit level)을 포함한 시스템 레벨(System level)에서의 시뮬레이션 해석 방법을 제안한다. 일반적인 전력전자 시스템의 설계 방법은 회로 레벨과 시스템 레벨에서 별도로 시뮬레이션하거나 이상적인 모델을 이용하여 시스템을 해석하여 왔으나, 이러한 시스템 설계 방법은 별도의 시제품을 제작하여 측정함으로써 시간과 금전적 손실이 있었다. 이러한 점을 보완하기 위해서 PSpice와 Simulink를 이용한 Co-Simulation방법을 제안한다.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.329-332
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• 2000

This paper proposed resource allocation algorithm for the minimum power consumption of functional unit in high level synthesis process as like DSP which is circuit to give many functional unit. In this paper, the proposed method though high level simulation find switching activity in circuit each functional unit exchange for binary sequence length and value bit are logic one value. To used the switching activity find the allocation with minimal power consumption, the proposed method visits all control steps one by one and determines the allocation with minimal power consumption at each control step.