• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.12
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• pp.75-84
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• 2001

Due to the high density of integration in current integrated circuit layouts, circuit elements must be designed to minimize the effect of parasitic elements and thereby minimize the factors which can degrade circuit performance. Thus, before making a chip, circuit designers should check whether the extracted netlist is correct, and verify from a simulation whether the circuit performance satisfies the design specifications. In this paper, we propose a new block disassembly technique which can extract the geometric parameters of stacked MOSFETs and the distributed RCs of layout blocks. After applying this to the layout of a folded-cascode CMOS operational amplifier, we verified the connectivity and the effect of the components by simulating the extracted netlist with HSPICE.

• Korean Journal of Materials Research
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• v.24 no.4
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• pp.186-193
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• 2014

A thin Cu seed layer for electroplating has been employed for decades in the miniaturization and integration of printed circuit board (PCB), however many problems are still caused by the thin Cu seed layer, e.g., open circuit faults in PCB, dimple defects, low conductivity, and etc. Here, we studied the effect of heat treatment of the thin Cu seed layer on the deposition rate of electroplated Cu. We investigated the heat-treatment effect on the crystallite size, morphology, electrical properties, and electrodeposition thickness by X-ray diffraction (XRD), atomic force microscope (AFM), four point probe (FPP), and scanning electron microscope (SEM) measurements, respectively. The results showed that post heat treatment of the thin Cu seed layer could improve surface roughness as well as electrical conductivity. Moreover, the deposition rate of electroplated Cu was improved about 148% by heat treatment of the Cu seed layer, indicating that the enhanced electrical conductivity and surface roughness accelerated the formation of Cu nuclei during electroplating. We also confirmed that the electrodeposition rate in the via filling process was also accelerated by heat-treating the Cu seed layer.

• Transactions on Electrical and Electronic Materials
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• v.15 no.3
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• pp.139-143
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• 2014

In this paper, an integrated low-voltage control circuit is introduced for a charge pump DC-DC boost converter. By exploiting the advantage of the integration of the feedback control circuit within CMOS technology, the charge pump boost converter offers a low-current operation with small ripple voltage. The error amplifier, comparator, and oscillator in the control circuit are designed with the supply voltage of 3.3 V and the operating frequency of 1.6~5.5 MHz. The charge pump converter with the 4 or 8 pump stages is measured in simulation. The test in the $0.35{\mu}m$ CMOS process shows that the load current and ripple ratio are controlled under 1 mA and 2% respectively. The output-voltage is obtained from 4.8 ~ 8.5 V with the supply voltage of 3.3 V.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.5
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• pp.431-438
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• 2005

In this paper, we propose the built-in current testing circuit for improving reliability As the integrated CMOS circuits in a chip are increased, the testability on design and fabrication should be considered to reduce the cost of testing and to guarantee the reliability In addition, the high degree of integration makes more failures which are different from conventional static failures and introduced by the short between transistor nodes and the bridging fault. The proposed built-in current testing method is useful for detecting not only these failures but also low current level failures and faster than conventional method. In normal mode, the detecting circuit is turned off to eliminate the degradation of CUT(Circuits Under Testing). The differential input stage in detecting circuit prevents the degradation of CUT in test mode. It is expected that this circuit improves the quality of semiconductor products, the reliability and the testability.

• Proceedings of the KIEE Conference
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• 2008.04c
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• pp.106-109
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• 2008

Piecewise linear diode models are widely used for large-signal circuit analyses, especially power electronic circuit simulations. When using a piecewise linear diode model for simulation, a switching method to select a proper one among linear models is needed. The conventional switching method keeps the previous ON, OFF state information, and applies different switching conditions according to the state. However, this method has difficulties especially in extending to multi-piecewise linear models. This paper presents a switching method which appropriately divides the v-i plane into regions and select a linear model according to the region where the operating point(the voltage and the current of the diode) belongs. This switching method is easily extended to multi-Piecewise linear models. An example using the tableau analysis and the backward Euler integration is presented for verification.

• Journal of the Optical Society of Korea
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• v.18 no.5
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• pp.564-568
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• 2014

We present a 25-Gb/s optical transmitter composed of a Si ring modulator and CMOS driver circuit. The Si ring modulator is realized with 220-nm Si-on-insulator process and the driver circuit with 65-nm CMOS process. The modulator and the driver are hybrid-integrated on the printed circuit board with bonding wires. The driver is designed so that the parasitic bonding wire inductance provides enhanced driver bandwidth. The transmitter successfully demonstrates 25-Gb/s operation.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.11
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• pp.140-148
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• 1993

High Integration ratio of CMOS circuits incredily increases the test cost during the design and fabrication processes because of the FET fault(Stuck-on faults and Stuck-off faults) which are due to the operational characteristics of CMOS circuits. This paper proposes a test generation algorithm for an arbitrarily large CMOS circuit, which can unify the test steps during the design and fabrication procedure and be applied to both static and dynaic circuits. This algorithm uses the logic equations set for the subroutines resulted from arbitrarily dividing the full circuit hierarchically or horizontally. Also it involves a driving procedure from output stage to input stage, in which to drive a test set corresponding to a subcircuit, only the subcircuits connected to that to be driven are used as the driving resource. With this algorithm the test cost for the large circuit such as VLSI can be reduced very much.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.583-586
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• 2009

A 14.1" XGA (1024${\times}$768) LCD panel with Integrated Black Data Insertion (IBDI) has been world first developed successfully based on the integrated amorphous Silicon TFT gate driver which we previously introduced. The notable features compared with the conventional integrated a-Si TFT gate driver circuit are that the circuit consists of Dual buffer, Carry buffer structure, and Q-node cross charging for stable signal scanning characteristic and prevention of coupling between signal lines.

• ETRI Journal
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• v.31 no.2
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• pp.209-214
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• 2009

In this paper, we propose a novel test methodology for the detection of catastrophic and parametric faults present in analog very large scale integration circuits. An automatic test pattern generation algorithm is proposed to generate piece-wise linear (PWL) stimulus using wavelets and a genetic algorithm. The PWL stimulus generated by the test algorithm is used as a test stimulus to the circuit under test. Faults are injected to the circuit under test and the wavelet coefficients obtained from the output response of the circuit. These coefficients are used to train the neural network for fault detection. The proposed method is validated with two IEEE benchmark circuits, namely, an operational amplifier and a state variable filter. This method gives 100% fault coverage for both catastrophic and parametric faults in these circuits.

• Proceedings of the KAIS Fall Conference
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• 2007.11a
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• pp.78-80
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• 2007

According to the development of VLSI integration technology and getting bigger the circuit size, it is a significant problem to verify systemized circuit. The faster and more accurate verification has very significant meaning in the field of electronic industry because it can yield the product comparably faster and reduce the trial and errors. In spite of the presence of various kind of Integrated Circuits it's not always easy to get the right part. Besides, it is hard to find a vendor for a small quantity consumers like who develop prototype applications. In this study, we've tried to get the logical signals from the PC based device we've developed that correspondents with the real ICs. It can emulate decoder ICs, multiplexers, demultiplexers and basic logic gates.