• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제51권5호
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• pp.242-248
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• 2002

It is important to develop new effective technologies to increase the interruption capacity and to reduce the size of a UB(Gas Circuit Breakers). Major design parameters such as nozzle geometries and interrupting chamber dimensions affect the cooling of the arc and the breaking performance. But it is not easy to test real GCB model in practice as in theory. Therefore, a simulation tool based on a computational fluid dynamics(CFD) algorithm has been developed to facilitate an optimization of the interrupter. Special attention has been paid to the supersonic flow phenomena between contacts and the observation of hat-gas flow for estimating the breaking performance. However, there are many difficult problems in calculating the flow characteristics in a GCB such as shock wave and complex geometries, which may be either static or in relative motion. Although a number of mesh generation techniques are now available, the generation of meshes around complicated, multi-component geometries like a GCB is still a tedious and difficult task for the computational fluid dynamics. This paper presents the CFD program using CFB-CAD integration technique based on Cartesian cut-cell method, which could reduce researcher's efforts to generate the mesh and achieve the accurate representation of the geometry designed by a CAD tools.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1444-1446
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• 2002

In this paper, we propose a new algorithm to calculate the maximum amount of available resource while preventing the outage to the currently serviced users not only in the home cell but also in adjacent cells. The effect of resource management in adjacent cells is simulated.

• 한국광학회지
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• 제18권3호
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• pp.185-189
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• 2007

평판형 AWG(Arrayed Waveguide Grating) 기술을 이용한 새로운 CWDM(Coarse Wavelength Division Multiplexer) 소자의 제작기술을 제안한다. 슬랩 도파로 입력단에 나팔형태를 갖는 도파로에 대하여 광전파방법(BPM)에 의한 전산모사 결과와 투과대역이 평탄화된 20 nm 간격의 CWDM 소자의 제작 결과를 보고한다. $0.75{\triangle}%$의 박막을 사용하였으며, 소자의 삽입손실은 가우시안 형태에 대하여 3.5 dB와 평탄화된 형태에 대하여 4.8 dB를 각각 얻었으며, 3 dB 대역폭은 각각 10 nm 및 13 nm 이상의 결과를 얻었다.

• 전자공학회논문지B
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• 제31B권4호
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• pp.155-165
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• 1994

An analog neural network circuit of rhigh density integration is introduced. It's prototype chip is designed in 3 by 3 mm2 die. It uses only one MOSFET to implement a synapse. The number of synapses per neuron can be expanded by cascading several chips. The influence of nonlinearity in synapses is analyzed. A formalization of the back propagation which can be applied to this circuit is shown. Some simulation results are shown and disscussed.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권6호
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• pp.658-663
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• 2015

In the previous work, we have proposed an integrate-and-fire neuron circuit and synaptic device based on the floating body MOSFET [1-3]. Integrate-and-Fire(I&F) neuron circuit emulates the biological neuron characteristics such as integration, threshold triggering, output generation, refractory period using floating body MOSFET. The synaptic device has short-term and long-term memory in a single silicon device. In this paper, we connect the neuron circuit and the synaptic device using current mirror circuit for summation of post synaptic pulses. We emulate spike-timing-dependent-plasticity (STDP) characteristics of the synapse using feedback voltage without controller or clock. Using memory device in the logic circuit, we can emulate biological synapse and neuron with a small number of devices.

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2002년도 학술대회논문집
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• pp.281-286
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• 2002

An existent hoist drive system is using each different drive equipment in control of Hoisting, traveling(T/L), traversing(T/S) driving, so there are much energy losses because of excessive weight. Also, power circuits are using relay contact, so working environment are frequent secession accident etc.. by shock on unfavorable condition, and there is danger of safety accident, maintenance has frequent problem and so on. To solve these problem, it is integrated each driving power supply in drive system for hoist control and drive, utility power supply etc.. by single device in this research. The power circuit is consisted of non-contact circuit applying to bidirectional voltage controller circuit using thyristor that is power semiconductor switching device

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• 제11B권3호
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• pp.112-118
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• 2001

In the near future, the voltage of power system for passenger vehicle will be changed to 42V from existing 14V./ Because of increasing power and voltage ratings used in the vehicle the motor drive system has high switching dv/dt and it generates electromagnetic interference (EMI) To solve these problems multi-level inverter system may be used The feature of multi-level inverter is the output voltage to be synthesized from several levels of voltage Because of this feature high switching dv/dt and EMI can be reduced in the multi-level inverter system But as the number of level is increased manufacturing cost is getting expensive and system size is getting large. Because of these disadvantages the application of multi-level inverter has been restricted only to high power drives. The method to reduce manufacturing cost and system size is to integrate circuit of multi-level inverter into a few chips But isolated power supply and signal isolation circuit using transformer or opto-coupler for drive circuit are obstacles to implement the integrated circuit (IC) In this paper a drive circuit of 4-level inverter suitable for integration to hybrid or one chip is proposed In the proposed drive circuit DC link voltage is used directly as the power source of each gate drive circuit NPN transistors and PNP transistors are used to isolate to transfer the control signals. So the proposed drive circuit needs no transformers and opto-couplers for electrical isolation of drive circuit and is constructed only using components to be implemented on a silicon wafer With th e proposed drive circuit 4- level inverter system will be possible to be implemented through integrated circuit technology Using the proposed drive circuit 4- level inverter system is constructed and the validity and characteristics of the proposed drive circuit are proved through the experiments.

• 한국지능시스템학회논문지
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• 제12권2호
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• pp.135-143
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• 2002

본 논문에서는 전류모드 CMOS의 기본회로를 이용해 다치 논리(Multiple Valued Logic) 연산기를 설계하고자 한다. 우선, 2진(binary)FFT(Fast courier Transform)를 확장해 다치 논리회로를 이용해서 고속 다치 FFT 연산기를 구현하였다. 다치논리회로를 이용해서 구현한 FFT연산은 기존의 2치 FFT과 비교를 해 본 결과 트랜지스터의 수를 상당히 줄일 수 있으며 회로의 간단함을 알 수가 있었다. 또한, 캐리 전파 없는 가산기론 구현하기 위해서 {0, 1, 2, 3}의 불필요한(redundant) 숫자 집합을 이용한 양의 수 표현을 FFT회로에 내부적으로 이용하여 결선의 감소와 VLSI 설계시 정규성과 규clr성으로 효과적이다. FFT 승산을 위해서는 승산기의 연산시간과 면적을 다치 LUT(Look Up Table)로 이용해 승산의 역할을 하였다. 마지막으로 이진시스템(binary system)과의 호환을 위해 다치 하이브리드형 FFT 프로세서를 제시하여 2진 4치 부호기와 4치 2진 복호기 및 전류모드 CMOS회로를 사용하여 상호 호환성을 갖도록 설계를 하였다.

• 전자공학회논문지SC
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• 제37권6호
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• pp.42-49
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• 2000

본 논문에서는 2ⁿ개의 노드를 갖는 DCG 특성에 대한 병렬 3치 논리회로를 설계하는 알고리즘을 제안하였다. 회로의 집적도를 높이기 위한 다양한 연구분야 중 전송선의 신호레벨을 증가시켜줌으로써 회로내의 배선밀도를 낮출 수 있으며 병렬신호전송을 통한 신호처리의 고속화, 회로의 특성을 만족시키며 최적화할 수 있는 회로설계알고리즘은 모두 고밀도 집적회로를 구현하기 위한 유용한 수단이 될 수 있다. 본 논문에서는 특히, 노드들의 개수가 2ⁿ개로 주어진 DCG에 대하여 그 특성을 행렬방정식으로 도출해내고 이를 통해 최적화 된 병렬3치 논리회로를 설계하는 과정을 정리하여 알고리즘으로 제안하였다. 또한, 설계된 회로의 동작특성을 만족하도록 DCG의 각 노드들의 코드를 할당하는 알고리즘도 제안하였다. 본 논문에서 제안된 알고리즘에 의해 회로결선의 감소와 처리속도 향상, 비용절감 측면에서 유용하다 할 수 있다.

• Journal of Power Electronics
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• 제12권3호
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• pp.439-447
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• 2012

In this paper, an input-series auxiliary power supply scheme is proposed, which is suitable for high input voltage and multiple-output applications. The power supply scheme is based on a two-transistor forward topology, all of the series modules have a common duty ratio, all the switches are turned on and off simultaneously, and the whole circuit has a single power transformer. It does not require an additional controller but still achieves efficient input voltage sharing (IVS) for each series module through its inherent transformer-integration strategy. The IVS process of this power supply scheme is analyzed in detail and the design considerations for the related parameters are given. Finally, a 100W multiple-output auxiliary power supply prototype is built, and the experimental results verify the feasibility of the proposed scheme and the validity of the theoretical analysis.