• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.10
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• pp.2237-2246
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• 2012

A bias circuit required for an oral sensor is manufactured inside the oral sensor chip to reduce its size and cost. The proposed DC-DC converter supplies the required reference and bias currents for their corresponding regulators by using IREF of the reference current generator. Their target voltages of the voltage regulators are regulated by the negative mechanism by generating their reference voltages required for their corresponding regulators. In addition, a constant current IB0/IB1 is supplied by being mirrored by a current mirror ratio and then VREF is generated. It is confirmed by measurements that the average volatge, ${\sigma}$, and $4{\sigma}$ of the designed DC-DC converter for intra oral sensors with a $0.18{\mu}m$ X-ray CMOS process are within their required ranges. And the line-pair pattern image shows a high-resolution characteristic without blurring. Also, a good oral image can be obtained.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.1-9
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• 2009

In this paper, a small area 12-bit 300MSPS CMOS Digital-to-Analog Converter(DAC) is proposed for display systems. The architecture of the DAC is based on a current steering 6+6 segmented type, which reduces non-linearity error and other secondary effects. In order to improve the linearity and glitch noise, an analog current cell using monitoring bias circuit is designed. For the purpose of reducing chip area and power dissipation, furthermore, a noble self-clocked switching logic is proposed. To verify the performance, it is fabricated with $0.13{\mu}m$ thick-gate 1-poly 6-metal N-well Samsung CMOS technology. The effective chip area is $0.26mm^2$ ($510{\mu}m{\times}510{\mu}m$) with 100mW power consumption. The measured INL (Integrated Non Linearity) and DNL (Differential Non Linearity) are within ${\pm}3LSB$ and ${\pm}1LSB$, respectively. The measured SFDR is about 70dB, when the input frequency is 15MHz at 300MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.39-50
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• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.673-684
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• 2003

A degenerated differential pair has been widely used as a standard topology for digitally programmable CMOS VGAs. A variable degeneration resistor has been implemented using a resistor string or R-2R ladder with MOSFET switches. However, in the VGAs using these conventional methods, low-voltage and high-speed operation is very hard to achieve due to the dc voltage drop over the degeneration resistor. To overcome this problem a new variable degeneration resistor is proposed where the dc voltage drop is almost removed. Using the proposed gain control scheme, a low-voltage and high-speed CMOS VGA is designed. HSPICE simulation results using a 0.25${\mu}{\textrm}{m}$ CMOS process parameters show that the designed VGA provides a 3dB bandwidth of 360MHz and a 80dB gain control range in 2dB step. Gain errors are less than 0.4dB at 200MHz and less than l.4dB at 300MHz. The designed circuit consumes 10.8mA from a 2.5V supply and its die area is 1190${\mu}{\textrm}{m}$${\times}$360${\mu}{\textrm}{m}$.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.80-87
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• 2013

A novel instrumentation amplifier(IA) using positive polarity current-conveyor(CCII+) for electronic measurement systems with low cost, wideband, and gain control with wide range is designed. The IA consists of two CCII+, three resistor, and an operational amplifier(op-amp). The principal of the operating is that the difference of two input voltages applied into two CCII+ used voltage and current follower converts into same currents, and then these current drive resistor of (+) terminal and feedback resistor of op-amp to obtain output voltage. To verify operating principal of the IA, we designed the CCII+ and used commercial op-amp LF356. Simulation results show that voltage follower used CCII+ has offset voltage of 0.21mV at linear range of ${\pm}$4V. The IA had wide gain range from -20dB to 60dB by variation of only one resistor and -3dB frequency for the gain of 60dB was 400kHz. The IA also has merits without matching of external resistor and controllable offset voltage using the other resistor. The power dissipation of the IA is 130mW at supply voltage of ${\pm}$5V.

• Korean Journal of Optics and Photonics
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• v.5 no.3
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• pp.423-430
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• 1994

We designed and fabricated the single mode fiber pigtailed DFB-LD module for 2.5 Gbps optical communication system. In the design of the DFB-LD module, we made the module divided into two parts of inner sub-module and outer 14-pin butterfly package and cylindrical shaped sub-module contain quasi confocal 2 lens system including optical isolator and electrical connection between these parts via hybrid substrate of bias T circuit. Laser welding was used to assemble the sub-module which requires accurate fixing between optical elements. The fabricated DFB-LD module showed optical coupling efficiency of 20% and - 3 dB small signal response of more than 2.6 GHz. We confirmed mechanical reliability of the module by temperature cycle test where the tested module exhibit optical power fluctuation of less than 10%. Finally we evaluated the performance of the fabricated DFB-LD module as light source of 2.5 Gbps optical communication system, sensitivity of - 30.2 dBm was obtained through 47 km optical fiber transmission under the criterion of $1\times10^{-10}$ BER and transmission penalties were 1.5 dB caused by extinction ratio and 1.0 dB caused by chromatic dispersion of normal single mode fiber. fiber.

• Journal of Engineering Education Research
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• v.10 no.3
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• pp.79-92
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• 2007

To enhance the excellence, effectiveness and economical efficiency in the learning process, we implement a hybrid educational system for engineering experiments where web-based virtual laboratory systems and distance education systems are properly integrated. In the first stage, we designed client/server distributed environment and developed web-based virtual laboratory systems for digital systems and electrical/electronic circuit experiments. The proposed virtual laboratory systems are composed of four important sessions and their management system: concept learning session, virtual experiment session, assessment session. With the aid of the management system every session is organically tied up together to achieve maximum learning efficiency. In the second stage, we have implemented efficient and cost-effective distant laboratory systems for practicing electric/electronic circuits, which can be used to eliminate the lack of reality occurred during virtual laboratory session. The use of simple and user-friendly design allows a large number of people to access our distant laboratory systems easily. Thus, self-guided advanced training is available even if a lot of expensive equipment will not be provided in the on-campus laboratories. The proposed virtual/distant laboratory systems can be used in stand-alone fashion, but to enhance learning efficiency we integrated them and developed a hybrid educational system for engineering experiments. Our hybrid education system provides the learners with interactive learning environment and a new approach for the delivery of engineering experiments.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.2 s.302
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• pp.27-36
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• 2005

This thesis proposed an effective encryption method for the DCT-based image/video contents and made it possible to operate in a high speed by implementing it as an optimized hardware. By considering the increase in the amount of the calculation in the image/video compression, reconstruction and encryption, an partial encryption was performed, in which only the important information (DC and DPCM coefficients) were selected as the data to be encrypted. As the result, the encryption cost decreased when all the original image was encrypted. As the encryption algorithm one of the multi-mode AES, DES, or SEED can be used. The proposed encryption method was implemented in software to be experimented with TM-5 for about 1,000 test images. From the result, it was verified that to induce the original image from the encrypted one is not possible. At that situation, the decrease in compression ratio was only $1.6\%$. The hardware encryption system implemented in Verilog-HDL was synthesized to find the gate-level circuit in the SynopsysTM design compiler with the Hynix $0.25{\mu}m$ CMOS Phantom-cell library. Timing simulation was performed by Verilog-XL from CadenceTM, which resulted in the stable operation in the frequency above 100MHz. Accordingly, the proposed encryption method and the implemented hardware are expected to be effectively used as a good solution for the end-to-end security which is considered as one of the important problems.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.11
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• pp.63-70
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• 2001

We demonstrate the MMIC (monolithic microwave integrated circuit) frequency doublers generating stable and low-cost 29 GHz local oscillator signals from 14.5 GHz input signals. These devices were designed and fabricated by using the M MIC integration process of $0.1\;{\mu}m$ gate-length PHEMTs (pseudomorphic high electron mobility transistors) and passive components. The measurements showed S11 or -9.2 dB at 145 GHz, S22 of -18.6 dG at 29 GHz and a minimum conversion loss of 18.2 dB at 14.5 GHz with an input power or 6 dBm. Fundamental signal of 14.5 GHz were suppressed below 15.2 dBe compared to the second harmonic signal at the output port, and the isolation characteristics of fundamental signal between the input and the output port were maintained above :i0 dB in the frequency range 10.5 GHz to 18.5 GHz. The chip size of the fabricated MMIC frequency doubler is $1.5{\times}2.2\;mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.28-37
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• 2010

In this paper, the IC (Integrated Circuit) for multi-channel asynchronous communication was designed by using FPGA and VHDL language. The existing chips for asynchronous communication that has been used commercially are composed of one to two channels. Therefore, when communication system with two channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 asynchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 256 bytes respectively and consequently high speed communication became possible. To detect errors between communications, it was designed with digital filter and check-sum logic and channel MUX logic so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. It was composed and simulated logic of VHDL described by using Cyclone II Series EP2C35F672C8 and QuartusII V8.1 of ALTERA company. In order to show the performance of designed IC, the test was conducted successfully in QuartusII simulation and experiment and the excellency was compared with TL16C550A of TI (Texas Instrument) company and ATmegal28 general-purpose micro controller of ATMEL company that are used widely as chips for asynchronous communication.