• Proceedings of the Korean Society of Marine Engineers Conference
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• 2002.05a
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• pp.147-152
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• 2002

This paper was studied on corrosion of heat exchanger tube for absorption refrigeration machine. In the 62 % lithium bromide solution at $60^{\circ}C$, polarization test of Cu, Al-brass, 10 % cupro nickel(90-10 % Cu-Ni) and 30 % cupronickel(70-30 % Cu-Ni) tube was carried out. And polarization behavior, polarization resistance characteristics, open circuit potential, anodic polarization of heat exchanger tube for absorption refrigeration machine were considered. The main results are as following: The open circuit potential of Al-brass tube becomes less noble than that of Cu tube, corrosion current density of that becomes lower than Cu tube. The open circuit potential of cupronickel tube is more noble than that of Cu tube, corrosion current density of that is controlled than Cu tube. The passivation critical current of 30 % Cu-Ni tube is lower than that of 10 % Cu-Ni tube, potential of passive region of that is more wide than 10 % Cu-Ni tube.

• 제어로봇시스템학회:학술대회논문집
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• 1999.10a
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• pp.281-283
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• 1999

This topic presents an inductor short turn testing. From the rudimentary principles, the quality factor(Q) decreases due to inductor short turn. Frequency response varies because of the variation of circuit inductance and resistance. In general, short turn circuit testing is performed by comparing the ratio of an inductance and resistance of inductor in that particular circuit. An alternative method can be done by considering the response of second order circuit which can give both dynamic and static testing, whereas static testing give an error results not more than 2 turns. For dynamic testing, the result is more accurate, which can test fur the short turn number form 1 turn onward.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.3
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• pp.139-144
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• 2003

We report the results of extensive mixed mode simulations and theoretical analysis to quantify the contribution of the edge direct tunneling (EDT) current on the total gate leakage current of 80nm NMOSFET with SiO2 gate dielectric. It is shown that EDT has a profound impact on basic analog circuit building blocks such as sample-hold (S/H) circuit and the current mirror circuit. A transistor design methodology with zero gate-source/drain overlap is proposed to mitigate the EDT effect. This results in lower voltage droop in S/H application and better current matching in current mirror application. It is demonstrated that decreasing the overlap length also improves the basic analog circuit performance metrics of the transistor. The transistor with zero gate-source/drain overlap, results in better transconductance, input resistance, output resistance, intrinsic gain and unity gain transition frequency.

• Journal of the Korean Institute of Telematics and Electronics
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• v.11 no.1
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• pp.15-22
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• 1974

A new ternary full adder using the current controlled negative-resistance circuit is described. The full adder is constructed from the modified-half-adder which was devised by making use of a negative resistance circuit. This full adder makes the number of its gates decrease and makes its own speed increase in comparison with the full adders which had been introduced previously. It is convenient to construct to the integrated circuit because transistor, SBD(Schottky Barrier Diode) and resistors were used as the circuit elements.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.50 no.1
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• pp.38-44
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• 2001

For double-circuit transmission line systems, an accurate digital distance relaying algorithm immune to the reactance effect is proposed. The apparent impedance calculated by the distance relay is influenced by the combined reactance effect of the fault resistance and the load current as well as the mutual coupling effect caused by the zero-sequence current of the adjacent parallel circuit. To compensate the magnitude and phase of the estimated impedance, this algorithm uses phase angle difference between the zero(positive) sequence of the both side of the system seperated by the fault point. The impedance measuring algorithm presented used a current distribution factor to compensate mutual coupling effect instead of the collected zero-sequence current of the adjacent parallel circuit.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.10
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• pp.33-46
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• 2015

In this paper, we predicts the analog and digital circuit performance of FinFETs that are scaled down following the ITRS(International technology roadmap for semiconductors). For accurate prediction of the circuit performance of scaled down devices, accurate parasitic resistance and capacitance analytical models are developed and their accuracies are within 2 % compared to 3D TCAD simulation results. The parasitic capacitance models are developed using conformal mapping, and the parasitic resistance models are enhanced to include the fin extension length($L_{ext}$) with respect to the default parasitic resistance model of BSIM-CMG. A new algorithm is developed to fit the DC characteristics of BSIM-CMG to the reference DC data. The proposed capacitance and resistance models are implemented inside BSIM-CMG to replace the default parasitic model, and SPICE simulations are performed to predict circuit performances such as $f_T$, $f_{MAX}$, ring oscillators and common source amplifier. Using the proposed parasitic capacitance and resistance model, the device and circuit performances are quantitatively predicted down to 5 nm FinFET transistors. As the FinFET technology scales, due to the improvement in both DC characteristics and the parasitic elements, the circuit performance will improve.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.11-16
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• 2017

The frequency dependent input resistance observed in RF MOSFETs is analyzed in detail by deriving pole and zero frequency equations from a simplified input equivalent circuit. Using this theoretical analysis, we find that the reduction effect of the input resistance in the low frequency region arises from the channel resistance between source and pinch-off region in the saturation region. This channel resistance effect on the low frequency reduction of the input resistance is physically validated by performing small-signal equivalent circuit modeling with varying the channel resistance.

• Journal of Satellite, Information and Communications
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• v.1 no.1
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• pp.54-58
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• 2006

A new design for easily controlling operating frequency of an antenna-integrated planar oscillator is introduced. The oscillator circuit of a broadband negative-resistance active part and a passive load including a patch antenna. The patch resonance is used for determining the oscillation frequency. This design reduces the possibility of mismatch between antenna radiation and oscillation frequencies. To achieve optimum output power, load-pull simulation for the negative-resistance circuit is used. The load-pull simulation shows the feed point and the delay of feed line can affect the oscillation power. Two negative-resistance circuits capable of supporting oscillation over full C-band and X-band are fabricated. The oscillation frequency, output power and phase noise for different patch antennas are measured.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.33 no.11
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• pp.456-463
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• 1984

The fast-rising high-voltage pulse generation circuit system of a theta pinch is both theoretically and experimentally investigated. The idealized model of this circuit system is a hybrid circuit system composed of three parts: a lumped circuit part being consisted of a capacitor bank and a spark switch connected in series, another lumped circuit part being consisted of the Blumlein transmission line, whose end load is the pinch coil. the voltage difference between two ends of the pinch coil is formulated by analyzing this hybrid circuit system by means of the law of the signal propagation in the transmission line and Kirchhoff's laws. The expedient numerical method for computer calculation is developed to generate the pulse profile of the voltage difference across the pinch coil. The period of the experimentally measured main pulse is a fourth of the theoretical one neglecting the resistance of the pinch coil. We attribute this discrepancy to the modelling in the theoretical calculation that hte resistance and inductance of the spark switch and capacitor bank are assumed to be constant through discharge. Therefore, we can see that the rise time of the imploding magnetic-field pulse is mainly dependent on the spark switch and capacitor bank.

• Nuclear Engineering and Technology
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• v.56 no.6
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• pp.2395-2403
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• 2024

With the rapid development of DC high voltage accelerator, higher requirements have been raised for the design of DC high voltage power supply, requiring more stable high voltage with lower output ripple. Therefore, it also puts forward higher requirements for the parameter design of the voltage doubling rectifier circuit, which is the core component of the DC high voltage power supply. In order to obtain output voltage with better performance, the effects of the working frequency, the stage capacitance and the load resistance on the output voltage of the voltage doubling rectifier circuit are studied in detail by simulation. It can be concluded that the higher the working frequency of the transformer, the larger the stage capacitance, the larger the load resistance and the better the output voltage performance in a certain range. Based on this, a 2.5 MV voltage doubling rectifier circuit driven by a 120 kHz frequency transformer is designed, developed and tested for the power supply of the neutron source device towards BNCT. Experimental results show that this voltage doubling rectifier circuit can satisfy the design requirements, laying a certain foundation for the engineering design of DC high voltage power supply of neutron source device.