• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.138-139
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• 2017

This paper describes the design and implementation of a trigger circuit which can be series connected with main pulse circuit for a xenon flash lamp driver. For generating high voltage, the trigger circuit is designed as an inductive energy storage pulsed power modulator with 2 state step-up circuit consisting of a boost converter and a flyback circuit. In order to guarantee pulse width, a resonant capacitor on the output side of the flyback circuit is designed. This capacitor limits the output voltage to protect the flyback switch. In addition, to protect another power supply of xenon flash lamp driver from trigger pulse, the high voltage transformer which can carry the full current of main pulse is designed. To verify the proposed design, the trigger circuit is developed with the specification of maximum 23 kV, 0.6 J/pulse output and tested with a xenon flash lamp driver consisting of a main pulse circuit and a simmer circuit.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.51-54
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• 1998

In this paper, we describe the design of the ATM Mux/Demux circuit between BSC and MSC for IMT-2000 Network. This ATM Mux/Demux circuit culd support 155Mbps optic interface with MSC. Using the CAM and DPRAM, this circuit performs ATM cell Mux/Demux functions in the BSC. MPC 860SAR processor was used for the signaling with MSC in this design.

• Journal of information and communication convergence engineering
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• v.7 no.2
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• pp.113-118
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• 2009

This paper is about design broadband impedance matching circuit for Coupler to improve power transfer efficiency in the power line communication (PLC) system. The Tchebycheff gain function algorithm is represented to design broadband matching circuit. A practical PLC Coupler impedance matching circuit is designed, and the characteristics for S11 and S21 of PLC coupler are enhanced comparing with unmatched one. This is done by maximizing the power transfer gain from modem to the load.

• Journal of information and communication convergence engineering
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• v.8 no.3
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• pp.258-262
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• 2010

This paper represents design broadband impedance matching circuit for Coupler to improve power transfer efficiency in the broadband power line communication(BPLC) systems. The Butterworth gain function equalizer is used to design broadband matching circuit. A practical PLC Coupler impedance matching circuit is designed, and the characteristics for S11 and S21 of PLC Coupler are enhanced comparing with unmatched one. This is done by maximizing the power transfer gain from modem to the load.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.333-336
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• 2001

This paper describes the design and implementation results of 40, 32, 24 and 16kbps ADPCM encoder and decoder circuit, based on the protocol CCITT G.726. We verified the ADPCM algorithm using C language and designed the RTL circuit with Verilog HDL. The circuit has been simulated by Verilog-XL, synthesized by Design Compiler and verified using Xilinx FPGA. Since the synthesized circuit includes a small number of gates, it is expected to be used as a core module in the digital voice and image processing SOC.

• Proceedings of the KIEE Conference
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• 1997.07a
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• pp.155-158
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• 1997

In design of current transformer, equivalent circuit parameters is obtained by electromagnetic analysis and used circuit simulation. Precise core secton area and turns of coil can be determined by circuit analysis. Therefore exact design of current transformer is possible by field and circuit analysis.

• Proceedings of the KSME Conference
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• 2001.11a
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• pp.859-864
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• 2001

In a vacuum circuit breaker mechanism, a spring-actuated linkage system is used to satisfy the desired opening and closing characteristics of electric contacts. Because the opening and the closing dynamics of electric contacts is determined by such a linkage system, the stiffness, free length and attachment points of a spring become the important design parameters. In this paper, based on the dynamic model of the circuit breaker using a multibody dynamic program ADAMS, a optimal design procedure of determining the spring design parameters is presented. The proposed procedure is applied to the design of an opening spring for satisfying the specified opening characteristics.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.2
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• pp.177-183
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• 2013

We describe a new method for selecting design variables for shape optimization of high-voltage gas circuit breaker using a Kriging meta-model and a genetic algorithm. Firstly we sample balance design variables using the Latin Hypercube Sampling. Secondly, we build meta-model using the Kriging. Thirdly, we search the optimal design variables using a genetic algorithm. To obtain the more exact design variable, we adopt the boundary shifting method. With the proposed optimization frame, we can get the improved interruption design and reduce the design time by 80%. We applied the proposed method to the optimization of multivariate optimization problems as well as shape optimization of a high - voltage gas circuit breaker.

• Journal of Practical Engineering Education
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• v.9 no.2
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• pp.99-106
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• 2017

The most important thing in STEAM education is to enhance students' interest and understanding of science and technology. In this paper, we propose basic circuit system design and control method applicable to STEAM fusion education. The circuit system design practice using the breadboard is designated as an essential curriculum in the corresponding department at the high school and college level in the domestic curriculum. However, there is a lack of STEAM convergence implementation examples that can easily understand circuit system design and control methods. Therefore, we proposed and tested a method to implement and control a media art type circuit system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.23-32
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• 2006

Fast and accurate power bus design (FAPUD) method for multi-layers high-speed digital boards is devised for the power supply network design tool for accurate and precise high speed board. FAPUD is constructed, based on two main algorithms of the PBEC (Path Based Equivalent Circuit) model and the network synthesis method. The PBEC model exploits simple arithmetic expressions of the lumped 1-D circuit model from the electrical parameters of a 2-D power distribution network. The circuit level design based on PBEC is carried with the proposed regional approach. The circuit level design directly calculates and determines the size of on-chip decoupling capacitors, the size and the location of off-chip decoupling capacitors, and the effective inductances of the package power bus. As a design output, a lumped circuit model and a pre-layout of the power bus including a whole decoupling capacitors are obtained after processing FAPUD. In the tuning procedure, the board re-optimization considering simultaneous switching noise (SSN) added by I/O switching can be carried out because the I/O switching effect on a power supply noise can be estimated over the operation frequency range with the lumped circuit model. Furthermore, if a design changes or needs to be tuned, FAPUD can modify design by replacing decoupling capacitors without consuming other design resources. Finally, FAPUD is accurate compared with conventional PEEC-based design tools, and its design time is 10 times faster than that of conventional PEEC-based design tools.